A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.