公开(公告)号：US12183722B2

公开(公告)日：2024-12-31

申请号：US17638039

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L49/02

Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

公开(公告)号：US12156331B2

公开(公告)日：2024-11-26

申请号：US17212016

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Khai Ern See ,  Jia Lin Liew ,  Tin Poay Chuah ,  Chee How Lim ,  Yi How Ooi

IPC: H05K1/02 ,  H01L21/3105 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42

Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.

公开(公告)号：US12135581B2

公开(公告)日：2024-11-05

申请号：US17955234

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Debendra Das Sharma ,  Daniel S. Froelich ,  Sean O. Stalley

IPC: G06F1/14 ,  G06F13/42 ,  H04B1/7073 ,  H04L69/14

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

公开(公告)号：US12119064B2

公开(公告)日：2024-10-15

申请号：US17114475

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Pawel Tomkiewicz ,  Jacek Jaworski

IPC: G11C11/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42 ,  G11C29/44

Abstract: A memory device including a memory array comprising a plurality of memory cells, respective memory cells each comprising a storage element comprising phase change memory programmable to three unique states; and a controller comprising circuitry, the controller to convert binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data and provide the ternary data to the memory array for storage.

公开(公告)号：US12085995B2

公开(公告)日：2024-09-10

申请号：US17033768

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Aleksander Magi ,  Evan P. Kuklinski ,  Shawn S. McEuen ,  David W. Browning ,  Juha Tapani Paavola

IPC: G06F1/16 ,  G06F3/02

CPC classification number: G06F1/1671 ,  G06F1/1652 ,  G06F3/0219

Abstract: Computing devices and peripherals having a dynamic curvature are disclosed. The base of a laptop can curve as the laptop lid is opened due to left and right base portions being pulled inward to a bisector of the base. Base portions can be pulled inwards by a bending strap pushed upwards by a lifter spring, by base hinges that rotate inwards, or a shape memory allow wire laced around pulleys that contract when heated. A display device with dynamic curvature can curve due to a rack and pinion linear actuator that extends or shortens adjustable rods housed in the display support. A base or display can be curved based on the context of the computer device or in response to certain events. The curvature of a base or display can be tunable by a user. Curved bases and displays can reduce wrist and eye strain.

公开(公告)号：US12079341B2

公开(公告)日：2024-09-03

申请号：US17354733

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Kapil Sood ,  Ioannis T. Schoinas ,  Yu-Yuan Chen ,  Raghunandan Makaram ,  David J. Harriman ,  Baiju Patel ,  Ronald Perez ,  Matthew E. Hoekstra ,  Reshma Lal

IPC: G06F21/57 ,  G06F9/50 ,  G06F21/53 ,  G06F21/72 ,  G06F21/85

CPC classification number: G06F21/57 ,  G06F9/505 ,  G06F21/53 ,  G06F21/72 ,  G06F21/85 ,  G06F2221/034

Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.

公开(公告)号：US12062410B2

公开(公告)日：2024-08-13

申请号：US17114407

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Ashraf B. Islam ,  Jaydip Bharatkumar Patel ,  Yasir Mohsin Husain ,  Balaji Srinivasan ,  Nicolas L. Irizarry

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.

公开(公告)号：US12056029B2

公开(公告)日：2024-08-06

申请号：US17115168

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F11/263 ,  G06F11/10 ,  G06F11/22 ,  G06F11/30 ,  G06F13/40

CPC classification number: G06F11/263 ,  G06F11/1004 ,  G06F11/221 ,  G06F11/2215 ,  G06F11/2247 ,  G06F11/3027 ,  G06F13/4027

Abstract: Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.

公开(公告)号：US12045135B2

公开(公告)日：2024-07-23

申请号：US18312759

申请日：2023-05-05

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy

IPC: G06F11/14 ,  G06F9/4401

CPC classification number: G06F11/1441 ,  G06F9/4403 ,  G06F9/4416

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

公开(公告)号：US12038854B2

公开(公告)日：2024-07-16

申请号：US17134089

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Jaya L. Jeyaseelan ,  Barnes Cooper ,  Abdul R. Ismail

IPC: G06F13/16 ,  G06F1/3234 ,  G06T1/20

CPC classification number: G06F13/1668 ,  G06F1/325 ,  G06T1/20 ,  G06F1/3265

Abstract: Techniques for controlling input/output (I/O) power usage are disclosed. In the illustrative embodiment, a power policy engine of a compute device monitors power usage, I/O data transfer rates, and temperature and determines when there should be a change in an I/O power setting. The I/O data transfer requires that the data be handled properly, causing the compute device to expend power on the I/O data transfer. The power policy engine may instruct a device driver, such as a driver of an I/O device, to change a data transfer rate of the I/O device, reducing the power the compute device spends handling I/O.