Invention Grant
- Patent Title: System for identifying a 3D chip
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Application No.: US15681135Application Date: 2017-08-18
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Publication No.: US10075694B2Publication Date: 2018-09-11
- Inventor: Alexandre Ayres , Bertrand Borot
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Seed IP Law Group LLP
- Priority: FR1750011 20170102
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H04N13/00 ; G11C5/04 ; G11C29/44 ; B42D25/42 ; B42D25/305

Abstract:
A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node. Sensing circuits are coupled to elementary elements of different levels. The outputs of the sensing circuits are used to generate a number, which serves as an identification number of the semiconductor chip.
Public/Granted literature
- US20180192027A1 SYSTEM FOR IDENTIFYING A 3D CHIP Public/Granted day:2018-07-05
Information query
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