A gate driving circuit includes: a plurality of stages configured to output a plurality of gate signals, wherein an Nth stage of the plurality of stages includes: an output pull-up unit including a control electrode connected to a first node, wherein the output pull-up unit is configured to increase an electric potential at the first node and is further configured to receive a clock signal and to output a gate signal of the Nth stage; a control node pull-up unit configured to charge the first node according to an (N−1)th control signal and an (N−2)th control signal; a control node pull-down unit configured to discharge a voltage of the first node as a first low voltage according to an (N+1)th control signal; and an output pull-down unit configured to discharge a gate signal of the Nth stage as the first low voltage according to the (N+1)th control signal.