Invention Grant
- Patent Title: Method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors
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Application No.: US15276588Application Date: 2016-09-26
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Publication No.: US10083742B2Publication Date: 2018-09-25
- Inventor: Wei Wu , Jawad B. Khan , Sanjeev N. Trika , Yi Zou
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Konrad Raynes Davda & Victor LLP
- Agent David W. Victor
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C11/56 ; G11C29/52 ; G06F11/10

Abstract:
Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.
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