公开(公告)号：US11526448B2

公开(公告)日：2022-12-13

申请号：US16586251

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Yi Zou ,  Gordon King

IPC: G06F12/0811 ,  G06F12/0873 ,  G06F12/02 ,  G06F13/16 ,  G06F12/0897

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

公开(公告)号：US11375250B2

公开(公告)日：2022-06-28

申请号：US17221253

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Yi Zou ,  Mohammad Ataur Rahman Chowdhury

IPC: H04N21/2343 ,  H04L65/61 ,  H04L65/60 ,  H04N21/234 ,  H04N21/426 ,  H04N21/63

Abstract: In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.

公开(公告)号：US20190278676A1

公开(公告)日：2019-09-12

申请号：US16424594

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Yi Zou ,  Arun Raghunath ,  Tushar Gohad ,  Anjaneya Reddy Chagam Reddy ,  Sujoy Sen

IPC: G06F11/20 ,  G06F13/16 ,  G06F13/40

Abstract: Technologies for fast distributed storage recovery include a distributed storage system that includes multiple controller nodes and multiple target nodes. Each controller node is coupled to a corresponding target node via a storage fabric. Each target node stores replica data. The system identifies a failed node and a corresponding node that was coupled to the failed node. If the failed node is a controller node, the corresponding node is a target node. If the failed node is a target node, the corresponding node is a controller node. The system instantiates a replacement node, adds the replacement node to the system, and couples the replacement node to the corresponding node. The system may direct a backup target node to copy replica data to the replacement target node via the storage fabric. Other embodiments are described and claimed.

公开(公告)号：US11550617B2

公开(公告)日：2023-01-10

申请号：US16907927

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Arun Raghunath ,  Yi Zou ,  Tushar Sudhakar Gohad ,  Anjaneya R. Chagam Reddy ,  Sujoy Sen

IPC: G06F9/46 ,  G06F3/06

Abstract: A method is described. The method includes performing the following with a storage end transaction agent within a storage sled of a rack mounted computing system: receiving a request to perform storage operations with one or more storage devices of the storage sled, the request specifying an all-or-nothing semantic for the storage operations; recognizing that all of the storage operations have successfully completed; after all of the storage operations have successfully completed, reporting to a CPU side transaction agent that sent the request that all of the storage operations have successfully completed.

公开(公告)号：US10972768B2

公开(公告)日：2021-04-06

申请号：US16457836

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Yi Zou ,  Mohammad Ataur Rahman Chowdhury

IPC: H04N21/2343 ,  H04N21/63 ,  H04N21/426 ,  H04N21/234

Abstract: In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.

公开(公告)号：US20190042091A1

公开(公告)日：2019-02-07

申请号：US15922502

申请日：2018-03-15

Applicant: Intel Corporation

Inventor： Arun Raghunath ,  Anjaneya Reddy Chagam Reddy ,  Sujoy Sen ,  Yi Zou

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16

Abstract: Technologies for providing efficient distributed data storage in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to receive, through a network and with the network interface controller, a data access request from a compute device. The data access request includes a data payload indicative of an object to be stored. The circuitry is also to map the object to a set of multiple data storage sleds for distributed storage of the object. Additionally, the circuitry is to send a write request with the object and an object identifier to the mapped data storage sleds to store the object in one or more data storage devices located on each data storage sled and concurrently send metadata without the object to one or more other compute sleds associated with the mapped data storage sleds. Other embodiments are also described and claimed.

公开(公告)号：US10043573B2

公开(公告)日：2018-08-07

申请号：US15228699

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： Wei Wu ,  Yi Zou ,  Jawad B. Khan ,  Xin Guo

IPC: G11C16/04 ,  G11C11/56 ,  G06F3/06 ,  G11C16/10

Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.

公开(公告)号：US20180060242A1

公开(公告)日：2018-03-01

申请号：US15254824

申请日：2016-09-01

Applicant: Intel Corporation

Inventor： Arun Raghunath ,  Michael P. Mesnier ,  Yi Zou

IPC: G06F12/0888 ,  G06F12/0891

CPC classification number: G06F12/0888 ,  G06F11/1076 ,  G06F12/0868 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/403 ,  H03M13/3761

Abstract: Methods and apparatus related to framework and/or methodology for selective caching of Erasure Coded fragments in a distributed storage system are described. In one embodiment, a plurality of fragments of a data object are generated. Each of the plurality of fragments is Erasure Coded (EC) prior to storage at a storage node of a plurality of storage nodes. Each of the plurality of fragments is transmitted with a caching hint to indicate whether that fragment is to be cached at the storage node. Other embodiments are also disclosed and claimed.

公开(公告)号：US11373406B2

公开(公告)日：2022-06-28

申请号：US16457818

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Yi Zou ,  Shao-Wen Yang ,  Gang Shen

IPC: G06K9/00 ,  G06V20/40 ,  G06F16/738

Abstract: In one embodiment, an apparatus comprises processing circuitry to: receive, via a network interface, a video stream comprising a plurality of video frames; identify a plurality of dependencies among the plurality of video frames; identify, based on the plurality of dependencies, a first subset of video frames to be transmitted using a first transmission method and a second subset of video frames to be transmitted using a second transmission method, wherein the first subset of video frames and the second subset of video frames are identified from the plurality of video frames, and wherein the first transmission method provides a higher quality of service than the second transmission method; transmit, via the network interface, the first subset of video frames to a corresponding destination using the first transmission method; and transmit, via the network interface, the second subset of video frames to the corresponding destination using the second transmission method.

公开(公告)号：US20220021917A1

公开(公告)日：2022-01-20

申请号：US17221253

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Yi Zou ,  Mohammad Ataur Rahman Chowdhury

IPC: H04N21/2343 ,  H04N21/234 ,  H04N21/426 ,  H04N21/63

Abstract: In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.