Invention Grant
- Patent Title: Impedance calibration circuit and semiconductor memory device including the same
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Application No.: US15424547Application Date: 2017-02-03
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Publication No.: US10083763B2Publication Date: 2018-09-25
- Inventor: Dong Wook Jang , Kwan Su Shon , Yo Han Jeong
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2016-0139145 20161025
- Main IPC: G11C29/50
- IPC: G11C29/50 ; H03K19/00

Abstract:
An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.
Public/Granted literature
- US20180114586A1 IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Public/Granted day:2018-04-26
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