Invention Grant
- Patent Title: Semiconductor device comprising memory circuit and selection circuit
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Application No.: US15011809Application Date: 2016-02-01
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Publication No.: US10090031B2Publication Date: 2018-10-02
- Inventor: Takahiko Ishizu , Kazuma Furutani , Keita Sato
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2015-022827 20150209
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G11C8/08 ; G11C8/12 ; G11C5/06

Abstract:
A novel semiconductor device, a semiconductor device with low power consumption, or a semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first selection circuit connected to a plurality of first memory circuits, a second selection circuit connected to a plurality of second memory circuits, and a third selection circuit connected to a plurality of third memory circuits, thereby being capable of conducting power gating of each of the first memory circuits, each of the second memory circuits, or each of the third memory circuits separately. Accordingly, the memory circuits to which data is not written or from which data is not read can be kept in a state where power supply thereto is stopped, so that power consumption of the semiconductor device can be reduced.
Public/Granted literature
- US20160232956A1 SEMICONDUCTOR DEVICE, CENTRAL PROCESSING UNIT, AND ELECTRONIC DEVICE Public/Granted day:2016-08-11
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