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公开(公告)号：US12107171B2
公开(公告)日：2024-10-01
申请号：US18133053
申请日：2023-04-11
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takahiko Ishizu , Kazuma Furutani
IPC: H01L29/00 , G11C5/06 , G11C11/40 , G11C11/405 , G11C11/4093 , G11C11/4096 , H01L29/786 , H10B12/00
CPC classification number: H01L29/7869 , G11C5/063 , G11C11/405 , G11C11/4093 , G11C11/4096 , H01L29/78696 , H10B12/50
Abstract: A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.
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公开(公告)号：US11309431B2
公开(公告)日：2022-04-19
申请号：US17053467
申请日：2019-05-07
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takahiko Ishizu , Kazuma Furutani
IPC: H01L29/78 , G11C11/40 , H01L29/786 , G11C5/06 , G11C11/405 , G11C11/4093 , G11C11/4096 , H01L27/108
Abstract: A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.
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公开(公告)号：US11908947B2
公开(公告)日：2024-02-20
申请号：US17628091
申请日：2020-07-27
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Munehiro Kozuma , Takahiko Ishizu , Takeshi Aoki , Masashi Fujita , Kazuma Furutani , Kousuke Sasaki
CPC classification number: H01L29/7869 , G06F7/5443 , G11C7/1069 , G11C7/1096 , G11C7/12 , G11C7/14 , H10B12/50 , H01L27/1225
Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
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Patent Agency Ranking
公开(公告)号：US11658247B2
公开(公告)日：2023-05-23
申请号：US17694787
申请日：2022-03-15
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takahiko Ishizu , Kazuma Furutani
IPC: H01L29/78 , G11C11/40 , H01L29/786 , G11C5/06 , G11C11/405 , G11C11/4093 , G11C11/4096 , H01L27/108
CPC classification number: H01L29/7869 , G11C5/063 , G11C11/405 , G11C11/4093 , G11C11/4096 , H01L27/10897 , H01L29/78696
Abstract: A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.
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公开(公告)号：US09817040B2
公开(公告)日：2017-11-14
申请号：US14625984
申请日：2015-02-19
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Masashi Tsubuku , Kazuma Furutani , Atsushi Hirose , Toshihiko Takeuchi
CPC classification number: G01R19/0092
Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g., a difference between the third potential and the fourth potential), and a value of current flowing between the first terminal of the transistor under test and the second terminal of the first transistor is calculated from the amount of the charge held by the node.
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公开(公告)号：US20140319518A1
公开(公告)日：2014-10-30
申请号：US14328818
申请日：2014-07-11
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Kazuma Furutani , Yoshinori Ieda , Yuto Yakubo , Kiyoshi Kato , Shunpei Yamazaki
IPC: H01L27/12
CPC classification number: H01L27/1214 , G11C11/403 , G11C16/0425 , G11C16/0433 , H01L27/1156 , H01L27/1225
Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.
Abstract translation: 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。
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公开(公告)号：US10090031B2
公开(公告)日：2018-10-02
申请号：US15011809
申请日：2016-02-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takahiko Ishizu , Kazuma Furutani , Keita Sato
Abstract: A novel semiconductor device, a semiconductor device with low power consumption, or a semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first selection circuit connected to a plurality of first memory circuits, a second selection circuit connected to a plurality of second memory circuits, and a third selection circuit connected to a plurality of third memory circuits, thereby being capable of conducting power gating of each of the first memory circuits, each of the second memory circuits, or each of the third memory circuits separately. Accordingly, the memory circuits to which data is not written or from which data is not read can be kept in a state where power supply thereto is stopped, so that power consumption of the semiconductor device can be reduced.
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公开(公告)号：US09136280B2
公开(公告)日：2015-09-15
申请号：US14328818
申请日：2014-07-11
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Kazuma Furutani , Yoshinori Ieda , Yuto Yakubo , Kiyoshi Kato , Shunpei Yamazaki
IPC: H01L27/12 , G11C16/04 , G11C11/403 , H01L27/115
CPC classification number: H01L27/1214 , G11C11/403 , G11C16/0425 , G11C16/0433 , H01L27/1156 , H01L27/1225
Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.
Abstract translation: 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。
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