Invention Grant
- Patent Title: Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process
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Application No.: US14977367Application Date: 2015-12-21
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Publication No.: US10096599B2Publication Date: 2018-10-09
- Inventor: Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/66 ; H01L29/40 ; H01L21/8234 ; H01L27/088 ; H01L29/49 ; H01L29/423 ; H01L29/78 ; H01L29/51

Abstract:
Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
Public/Granted literature
- US20160111426A1 METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS Public/Granted day:2016-04-21
Information query
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