A method of laying out a semiconductor device includes arranging a flip-flop in the semiconductor device, and rearranging the flip-flop to a selected location in the semiconductor device. The flip-flop may be configured to receive a clock from a clock gating cell through a clock line, to receive an input signal through an input line, and to output an output signal through an output line. The flip-flop may be rearranged based on a length of the clock line, the number of times the clock line is toggled per reference time, a length of the input line, a length of the output line, and at least one of: the number of times that the input signal is toggled per the reference time, and the number of times that the output signal is toggled per the reference time.