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公开(公告)号:US12074461B2
公开(公告)日:2024-08-27
申请号:US17705805
申请日:2022-03-28
发明人: Takashi Taya
摘要: A contactless power supply device contactless power supply device includes a power transmission module and a power reception module. The power transmission module includes a resonance circuit. The resonance circuit includes a power transmission coil generating a high-frequency magnetic field. The power reception module includes a resonance circuit. The resonance circuit includes a power reception coil generating a high frequency current by the high-frequency magnetic field. At least one of the power transmission module and the power reception module includes a relative movement detection unit that detects an amplitude change of a high-frequency voltage corresponding to the high frequency current flowing through the at least one resonance circuit of the power transmission module or the power reception module and outputs an output signal indicating a physical relative movement of the power transmission coil and the power reception coil.
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公开(公告)号:US11990114B2
公开(公告)日:2024-05-21
申请号:US17614496
申请日:2020-05-29
发明人: Hiroji Akahori
CPC分类号: G10K15/02 , B60Q5/008 , H04R1/025 , H04R2499/13
摘要: The present invention generates data series indicating respective combined-wave data pieces by a first step of obtaining a reference time length as a reference of a time length of one combined wave, a sampling interval time, and a frequency fluctuation rate, a second step of calculating a total number of samples in the data series indicating the one combined wave on the basis of the reference time length, the sampling interval time, and the frequency fluctuation rate, a third step of calculating a rotation angle with respect to the sampling interval time on the basis of the total number of samples for each of plural sound data pieces, a fourth step of calculating combined values for the total number of samples, the combined values being obtained by combining respective values of the plural sound data pieces, the values being calculated on the basis of the rotation angles for the respective sampling interval times, a fifth step of generating a series of the combined values for the total number of samples for the respective sampling time intervals as a data series of the one combined-wave data piece, and performing a sequence of the processes of the second to the fifth steps by a predetermined times while changing the frequency fluctuation rate every time when the sequence of the processes is executed once.
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公开(公告)号:US11942928B2
公开(公告)日:2024-03-26
申请号:US17955049
申请日:2022-09-28
发明人: Suguru Kawasoe
CPC分类号: H03K17/223 , G05F3/262
摘要: A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.
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公开(公告)号:US11929432B2
公开(公告)日:2024-03-12
申请号:US17097115
申请日:2020-11-13
发明人: Kazuya Uda
IPC分类号: H01L29/78 , H01L29/06 , H01L29/08 , H01L29/423
CPC分类号: H01L29/7825 , H01L29/0607 , H01L29/0865 , H01L29/0882 , H01L29/4236 , H01L29/7835
摘要: A semiconductor device including a source region formed at one main face of a semiconductor substrate; a drain region formed at the one main face and connected to the source region through a channel region; a gate electrode formed above the channel region; a drift layer formed at the one main face at a position between a lower portion of the gate electrode and the drain region; a trench including an opening in which one end is at the lower portion of the gate electrode and another end is at a position adjacent to the drain region, the trench being formed in the semiconductor substrate at a predetermined depth from the one main face to cut vertically across the drift layer; and an electrical field weakening portion, provided at vicinity of the one end, that weaken an electrical field generated between the source region and the drain region.
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公开(公告)号:US11894447B2
公开(公告)日:2024-02-06
申请号:US17476558
申请日:2021-09-16
发明人: Tetsuya Yamamoto
IPC分类号: H01L21/66 , H01L21/3213 , H01L29/66 , H01L29/423 , H01L29/788 , H01L21/266
CPC分类号: H01L29/66825 , H01L21/266 , H01L21/32139 , H01L29/42328 , H01L29/788 , H01L29/42324 , H01L29/42332 , H01L29/42344
摘要: A method for manufacturing a semiconductor device includes: implanting a P-type impurity from a region where the first conductor film is formed toward an inside of the semiconductor substrate with a first acceleration energy; forming a nitride film provided with a first opening on the first conductor film; forming an insulating film with a second opening from which the first conductor film is exposed; forming a second conductor film to fill the second opening of the insulating film; removing the nitride film and a portion of the first conductor film positioned below the nitride film to expose the oxide film in a peripheral area of a formation region of the insulating film; and implanting the P-type impurity from a region from which the oxide film is exposed toward an inside of the semiconductor substrate with a second acceleration energy smaller than the first acceleration energy.
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公开(公告)号:US11763894B2
公开(公告)日:2023-09-19
申请号:US17949752
申请日:2022-09-21
发明人: Dong-Hun Kwak
IPC分类号: G11C16/26 , G11C16/08 , G11C16/10 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04 , H10B41/27 , H10B43/27
CPC分类号: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3459 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H10B43/27 , H01L2224/05147 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.
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公开(公告)号:US11733204B2
公开(公告)日:2023-08-22
申请号:US17356648
申请日:2021-06-24
发明人: Kazuhiro Nakano
IPC分类号: G01N27/414 , G01N27/30
CPC分类号: G01N27/414 , G01N27/301
摘要: A reference electrode including a casing through which one face at one side of a liquid junction that leaches an internal liquid is exposed, the casing being provided with an overhang portion that hangs out on the one face side of the liquid junction and prevents separation of the liquid junction from the casing; and an open portion that leaves a space on the one side of the liquid junction open toward a lateral direction along the one face.
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公开(公告)号:US11720588B2
公开(公告)日:2023-08-08
申请号:US17347737
申请日:2021-06-15
发明人: Bruce R. Henderson , Anthony Gibson
IPC分类号: G06F16/00 , G06F7/00 , G06F16/25 , G06F16/24 , G06F16/29 , G06F16/951 , G06F16/958 , G06F16/2453 , G06F16/2455 , G06Q10/10
CPC分类号: G06F16/258 , G06F16/24 , G06F16/24544 , G06F16/24556 , G06F16/25 , G06F16/29 , G06F16/951 , G06F16/972 , G06Q10/10
摘要: A method for communicating data includes interfacing different data sources to stand-alone software agents customized for the different data sources. The method also providing selected source data to the stand-alone software agents to generate first-stage data feeds in a neutral format in accordance with the customization. The selected source data is dynamically selected from within the data sources, and transformed into the first-stage data feeds in the neutral format. The stand-alone software agents send the first-stage data feeds to an aggregation agent. The aggregation agent generates for a user and based on specified criteria, a second-stage output as a composite of selected source data from the first-stage data feeds.
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公开(公告)号:US11710518B2
公开(公告)日:2023-07-25
申请号:US17321769
申请日:2021-05-17
发明人: Young-Wook Kim , Hyuk-Joon Kwon , Sang-Keun Han , Bok-Yeon Won
IPC分类号: G11C5/06 , G11C11/4091 , G11C5/02 , G11C7/02 , G11C11/4094 , G11C11/4097 , G11C11/4096 , G11C11/408 , G11C7/06
CPC分类号: G11C11/4091 , G11C5/025 , G11C7/02 , G11C11/4094 , G11C11/4097 , G11C5/02 , G11C5/06 , G11C7/06 , G11C11/4082 , G11C11/4087 , G11C11/4096 , G11C2207/002
摘要: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.
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公开(公告)号:US11700005B2
公开(公告)日:2023-07-11
申请号:US17509540
申请日:2021-10-25
发明人: Kangyeop Choo , Insung Kim , Wooseok Kim , Taeik Kim , Sunghyuck Lee , Chanyoung Jeong
CPC分类号: H03L7/0891 , H03L7/101
摘要: A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.
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