Invention Grant
- Patent Title: Method for creating alternate hardmask cap interconnect structure with increased overlay margin
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Application No.: US15529483Application Date: 2014-12-24
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Publication No.: US10109583B2Publication Date: 2018-10-23
- Inventor: Robert L. Bristol , Manish Chandhok , Jasmeet S. Chawla , Florian Gstrein , Eungnak Han , Rami Hourani , Kevin Lin , Richard E. Schenker , Todd R. Younkin
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2014/072393 WO 20141224
- International Announcement: WO2016/105423 WO 20160630
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/532

Abstract:
Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.
Public/Granted literature
- US20170263551A1 NOVEL METHOD FOR CREATING ALTERNATE HARDMASK CAP INTERCONNECT STRUCTURE WITH INCREASED OVERLAY MARGIN Public/Granted day:2017-09-14
Information query
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