公开(公告)号：US10256141B2

公开(公告)日：2019-04-09

申请号：US15744018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Todd R. Younkin ,  Eungnak Han ,  Jasmeet S. Chawla ,  Marie Krysak ,  Hui Jae Yoo ,  Tristan A. Tronic

IPC: H01L21/331 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US10109583B2

公开(公告)日：2018-10-23

申请号：US15529483

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Robert L. Bristol ,  Manish Chandhok ,  Jasmeet S. Chawla ,  Florian Gstrein ,  Eungnak Han ,  Rami Hourani ,  Kevin Lin ,  Richard E. Schenker ,  Todd R. Younkin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

公开(公告)号：US10269622B2

公开(公告)日：2019-04-23

申请号：US15529479

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Rami Hourani ,  Michael J. Leeson ,  Todd R. Younkin ,  Eungnak Han ,  Robert L. Bristol

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  G03F7/00 ,  G03F7/16 ,  H01L21/027

Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.

公开(公告)号：US10971394B2

公开(公告)日：2021-04-06

申请号：US16284568

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Todd R. Younkin ,  Eungnak Han ,  Jasmeet S. Chawla ,  Marie Krysak ,  Hui Jae Yoo ,  Tristan A. Tronic

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US10950501B2

公开(公告)日：2021-03-16

申请号：US15772013

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Todd R. Younkin ,  Eungnak Han ,  Shane M. Harlson ,  James M. Blackwell

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  G03F7/00 ,  G03F7/004 ,  G03F7/16 ,  H01L21/027

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive. The method also includes irradiating and developing select locations of the third segregated block component to provide via openings over the metal lines of the lower metallization layer.

公开(公告)号：US10678137B2

公开(公告)日：2020-06-09

申请号：US15504469

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Todd R. Younkin ,  Sang H. Lee ,  Charles H. Wallace

IPC: H01L21/768 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  G03F7/00 ,  G03F7/09

Abstract: Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.