公开(公告)号：US12237223B2

公开(公告)日：2025-02-25

申请号：US17033483

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Paul A. Nyhus ,  Charles H. Wallace ,  Manish Chandhok ,  Mohit K Haran ,  Gurpreet Singh ,  Eungnak Han ,  Florian Gstrein ,  Richard E. Schenker ,  David Shykind ,  Jinnie Aloysius ,  Sean Pursel

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L27/088

Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.

公开(公告)号：US11721580B2

公开(公告)日：2023-08-08

申请号：US16435902

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Michael Harper ,  Suzanne S. Rich ,  Charles H. Wallace ,  Curtis Ward ,  Richard E. Schenker ,  Paul Nyhus ,  Mohit K. Haran ,  Reken Patel ,  Swaminathan Sivakumar

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/033

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/823412 ,  H01L21/823475

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

公开(公告)号：US11373900B2

公开(公告)日：2022-06-28

申请号：US17025087

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Robert L. Bristol ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/528

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US10937689B2

公开(公告)日：2021-03-02

申请号：US16465510

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Satyarth Suri ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

Abstract: In one embodiment, a trench may be formed in a dielectric surface, and the trenched may be lined with a liner. The trench may be filled with a metal, and the metal may be recessed below an opening of the trench. The liner may be converted into a dielectric, and a hard mask may be deposited into the trench.

公开(公告)号：US10804141B2

公开(公告)日：2020-10-13

申请号：US16092722

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Robert L. Bristol ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/528

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US11990403B2

公开(公告)日：2024-05-21

申请号：US17218080

申请日：2021-03-30

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Richard E. Schenker ,  Jeffery D. Bielefeld ,  Rami Hourani ,  Manish Chandhok

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5226

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US11837644B2

公开(公告)日：2023-12-05

申请号：US16579069

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Richard Vreeland ,  Giselle Elbaz ,  Manish Chandhok ,  Richard E. Schenker ,  Gurpreet Singh ,  Florian Gstrein ,  Nafees Kabir ,  Tristan A. Tronic ,  Eungnak Han

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/7851

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US10553532B2

公开(公告)日：2020-02-04

申请号：US15529484

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Richard E. Schenker ,  Manish Chandhok ,  Robert L. Bristol ,  Mauro J. Kobrinsky ,  Kevin Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/532

Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.

公开(公告)号：US10032643B2

公开(公告)日：2018-07-24

申请号：US15528736

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmeet S. Chawla ,  Ruth A. Brain ,  Richard E. Schenker ,  Kanwal Jit Singh ,  Alan M. Myers

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/48 ,  H01L23/522

Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.

公开(公告)号：US09793163B2

公开(公告)日：2017-10-17

申请号：US14912036

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Florian Gstrein ,  Richard E. Schenker ,  Paul A. Nyhus ,  Charles H. Wallace ,  Hui Jae Yoo

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.