Invention Grant
- Patent Title: CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel
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Application No.: US15024348Application Date: 2013-12-16
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Publication No.: US10109711B2Publication Date: 2018-10-23
- Inventor: Stephen M Cea , Roza Kotlyar , Harold W Kennel , Anand S Murthy , Glenn A Glass , Kelin J Kuhn , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- International Application: PCT/US2013/075452 WO 20131216
- International Announcement: WO2015/094167 WO 20150625
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L27/092 ; H01L29/161 ; H01L29/04 ; H01L29/66 ; H01L29/778 ; H01L29/165 ; H01L21/8238 ; H01L21/84 ; H01L27/12

Abstract:
Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
Public/Granted literature
- US20160240616A1 NMOS AND PMOS STRAINED DEVICES WITHOUT RELAXED SUBSTRATES Public/Granted day:2016-08-18
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