公开(公告)号：US09202889B2

公开(公告)日：2015-12-01

申请号：US13931678

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A Glass ,  Thomas Hoffman

IPC: H01L29/43 ,  H01L29/66 ,  H01L21/285 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract translation: 本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻 。 基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。 可以掺杂硅锗以进一步调整其电性能。 降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

公开(公告)号：US10109711B2

公开(公告)日：2018-10-23

申请号：US15024348

申请日：2013-12-16

Applicant: INTEL CORPORATION

Inventor： Stephen M Cea ,  Roza Kotlyar ,  Harold W Kennel ,  Anand S Murthy ,  Glenn A Glass ,  Kelin J Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/161 ,  H01L29/04 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.