公开(公告)号：US09935107B2

公开(公告)日：2018-04-03

申请号：US15024347

申请日：2013-12-16

Applicant: INTEL CORPORATION

Inventor： Stephen M Cea ,  Roza Kotlyar ,  Harold W Kennel ,  Kelin J Kuhn ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.

公开(公告)号：US10109711B2

公开(公告)日：2018-10-23

申请号：US15024348

申请日：2013-12-16

Applicant: INTEL CORPORATION

Inventor： Stephen M Cea ,  Roza Kotlyar ,  Harold W Kennel ,  Anand S Murthy ,  Glenn A Glass ,  Kelin J Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/161 ,  H01L29/04 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.