- 专利标题: Wafer level chip scale package with encapsulant
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申请号: US14861843申请日: 2015-09-22
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公开(公告)号: US10147645B2公开(公告)日: 2018-12-04
- 发明人: Navas Khan Oratti Kalandar , Nishant Lakhera , Akhilesh K. Singh
- 申请人: FREESCALE SEMICONDUCTOR, INC.
- 申请人地址: US TX Austin
- 专利权人: NXP USA, Inc.
- 当前专利权人: NXP USA, Inc.
- 当前专利权人地址: US TX Austin
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L29/08 ; H01L21/78 ; H01L21/56 ; H01L21/304 ; H01L23/31 ; H01L23/00
摘要:
A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.
公开/授权文献
- US20170084491A1 WAFER LEVEL CHIP SCALE PACKAGE WITH ENCAPSULANT 公开/授权日:2017-03-23
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