公开(公告)号：US09953904B1

公开(公告)日：2018-04-24

申请号：US15333580

申请日：2016-10-25

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Navas Khan Oratti Kalandar ,  Akhilesh Kumar Singh ,  Nishant Lakhera

IPC分类号： H01L23/495 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L23/49568 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49551 ,  H01L23/49575 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012

摘要： An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.

公开(公告)号：US10147645B2

公开(公告)日：2018-12-04

申请号：US14861843

申请日：2015-09-22

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Navas Khan Oratti Kalandar ,  Nishant Lakhera ,  Akhilesh K. Singh

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304 ,  H01L23/31 ,  H01L23/00

摘要： A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.

公开(公告)号：US09691637B2

公开(公告)日：2017-06-27

申请号：US14877467

申请日：2015-10-07

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Navas Khan Oratti Kalandar ,  Nishant Lakhera ,  Akhilesh K. Singh

IPC分类号： H01L21/56 ,  H01L21/78

CPC分类号： H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L23/16 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.

公开(公告)号：US09947614B2

公开(公告)日：2018-04-17

申请号：US15064689

申请日：2016-03-09

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Navas Khan Oratti Kalandar ,  Nishant Lakhera ,  Boon Yew Low ,  Akhilesh Singh

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/02 ,  H01L23/31

CPC分类号： H01L23/49575 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L25/105

摘要： A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.

公开(公告)号：US20180053753A1

公开(公告)日：2018-02-22

申请号：US15237827

申请日：2016-08-16

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Akhilesh Kumar Singh ,  Nishant Lakhera ,  Navas Khan Oratti Kalandar

IPC分类号： H01L25/10 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2224/48227 ,  H01L2924/00012

摘要： A stackable package assembly and method of manufacturing is provided. The method includes attaching a plurality of interconnect balls to a first surface of a substrate, and encapsulating the first surface of the substrate and the plurality of interconnect balls with an encapsulant. A trench is formed in a first surface of the encapsulant exposing a portion the interconnect balls. An interposer is provided having a first interconnect layer. An assembly is formed by attaching connection sites of a first interconnect layer to the exposed portion of the interconnect balls, the first surface of the second substrate extending into the trench.

公开(公告)号：US09721928B1

公开(公告)日：2017-08-01

申请号：US15141628

申请日：2016-04-28

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Navas Khan Oratti Kalandar ,  Lan Chu Tan ,  Chetan Verma

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L23/3128 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92127 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2224/45099 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85

摘要： A packaged IC device in which a die is sandwiched between first and second substrates such that (i) peripheral electrical contact pads of the die are wire bonded to the first substrate, e.g., for routing functional input/output signals, and (ii) core-area electrical contact pads of the die are connected to the second substrate in a flip-chip arrangement, e.g., for routing one or more power supply voltages to the core area of the die. The second substrate has a shape and position that (i) expose the peripheral electrical contact pads of the die for unencumbered machine-implemented wire bonding during the assembly process, and (ii) enable direct electrical connections between the first and second substrates outside the footprint of the die, e.g., by way of the corresponding solder bumps attached between the two substrates.

公开(公告)号：US09508632B1

公开(公告)日：2016-11-29

申请号：US14749243

申请日：2015-06-24

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Navas Khan Oratti Kalandar ,  Nishant Lakhera ,  Varughese Mathew ,  Akhilesh K. Singh

IPC分类号： H01L23/495 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49537 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/023 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/08145 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/3303 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06527 ,  H01L2225/1011 ,  H01L2225/1041 ,  H01L2225/1047 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19102 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a plurality of re-routed lead fingers attached to the lead frame. The plurality of leads has a first pitch. The first end of each re-routed lead finger is attached to a lead of the plurality of leads. Each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame. The second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.

摘要翻译： 半导体结构包括具有标志和多个引线的引线框架，附接到所述标记的第一主表面的半导体管芯以及附接到引线框架的多个重新布线的引线指示器。 多个引线具有第一间距。 每个重新布线的引线指的第一端附接到多个引线的引线。 每个重新布线的引线指在半导体管芯上延伸，使得每个重新布线的引线指的第二端在引线框架的标志之上并与之分开。 多个重新布线的引线指的第二端具有不同于第一间距的第二间距。