- 专利标题: Efficient validation of transactional memory in a computer processor
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申请号: US15265939申请日: 2016-09-15
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公开(公告)号: US10169181B2公开(公告)日: 2019-01-01
- 发明人: Vinod Bussa , Manoj Dusanapudi , Shakti Kapoor
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Martin & Associates, LLC
- 代理商 Bret J. Petersen
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/273 ; G06F11/22 ; G06F11/36 ; G06F11/263 ; G06F11/16
摘要:
A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that the transactional memory test proceeds further in the transaction mode if the transaction is successful. In contrast, if there is a failure of the transaction, then the transactional memory test is executed in the non-transaction state. The transactional memory test stresses both transaction success and transaction failure cases of the processor for more efficient validation of the computer processor. Also, when checking the correctness of the test case the correct result remains the same whether the transaction passes or fails to simplify verification.
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