公开(公告)号：US20200150961A1

公开(公告)日：2020-05-14

申请号：US16743628

申请日：2020-01-15

申请人： International Business Machines Corporation

发明人： Shakti Kapoor ,  Karen E. Yokum ,  John A. Schumann

IPC分类号： G06F9/30 ,  G06F12/0895 ,  G06F11/34 ,  G06F11/30

摘要： A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.

公开(公告)号：US10261917B2

公开(公告)日：2019-04-16

申请号：US15851936

申请日：2017-12-22

申请人： International Business Machines Corporation

发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F12/10 ,  G06F12/1045 ,  G06F12/0808 ,  G06F12/1027 ,  G06F11/263 ,  G06F12/1009 ,  G06F12/0831

摘要： A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

公开(公告)号：US20190079773A1

公开(公告)日：2019-03-14

申请号：US15704759

申请日：2017-09-14

申请人： International Business Machines Corporation

发明人： Shakti Kapoor

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F3/06

摘要： Embodiments of the invention are directed to methods for handling cache. The method includes retrieving a plurality of instructions from a cache. The method further includes placing the plurality of instructions into an instruction fetch buffer. The method includes retrieving a first instruction of the plurality of instructions from the instruction fetch buffer. The method includes executing the first instruction. The method includes retrieving a second instruction from the plurality of instructions from the instruction fetch buffer unless a back invalidate is received from the cache. Thereafter executing the second instruction without refreshing the instruction fetch buffer from the cache.

公开(公告)号：US20190050314A1

公开(公告)日：2019-02-14

申请号：US16141971

申请日：2018-09-26

申请人： International Business Machines Corporation

发明人： Manoj Dusanapudi ,  Shakti Kapoor ,  Nelson Wu

IPC分类号： G06F11/30 ,  G06F12/1081 ,  G06F13/28 ,  G06F13/10 ,  G06F11/26 ,  G06F11/263 ,  G06F11/22

摘要： A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

公开(公告)号：US10169181B2

公开(公告)日：2019-01-01

申请号：US15265939

申请日：2016-09-15

申请人： International Business Machines Corporation

发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F11/36 ,  G06F11/263 ,  G06F11/16

摘要： A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that the transactional memory test proceeds further in the transaction mode if the transaction is successful. In contrast, if there is a failure of the transaction, then the transactional memory test is executed in the non-transaction state. The transactional memory test stresses both transaction success and transaction failure cases of the processor for more efficient validation of the computer processor. Also, when checking the correctness of the test case the correct result remains the same whether the transaction passes or fails to simplify verification.

公开(公告)号：US09940226B2

公开(公告)日：2018-04-10

申请号：US15165007

申请日：2016-05-26

申请人： International Business Machines Corporation

发明人： Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F12/0837 ,  G06F12/084

CPC分类号： G06F11/3688 ,  G06F11/3684 ,  G06F12/0837 ,  G06F12/084 ,  G06F2212/1008

摘要： A system and method synchronizes heterogeneous agents in a computer system with a software synchronization mechanism. Agents of the computer system connected to a common memory, including agents lacking a hardware synchronization system, can be synchronized with the software synchronization mechanism. The synchronized agents can cause collisions on the same cache line in order to stress test the memory of the system. Each agent updates a first array to indicate it has arrived at the synchronization. After all the agents have arrived, each agent then updates a second array to announce its exit.

公开(公告)号：US20180074926A1

公开(公告)日：2018-03-15

申请号：US15265939

申请日：2016-09-15

申请人： International Business Machines Corporation

发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F11/273 ,  G06F11/22

CPC分类号： G06F11/273 ,  G06F11/167 ,  G06F11/2236 ,  G06F11/2273 ,  G06F11/263 ,  G06F11/3688

摘要： A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that the transactional memory test proceeds further in the transaction mode if the transaction is successful. In contrast, if there is a failure of the transaction, then the transactional memory test is executed in the non-transaction state. The transactional memory test stresses both transaction success and transaction failure cases of the processor for more efficient validation of the computer processor. Also, when checking the correctness of the test case the correct result remains the same whether the transaction passes or fails to simplify verification.

公开(公告)号：US20180052795A1

公开(公告)日：2018-02-22

申请号：US15242922

申请日：2016-08-22

申请人： International Business Machines Corporation

发明人： Shakti Kapoor ,  Grace Y. Liu ,  Karen E. Yokum

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F9/38 ,  G06F9/30 ,  G06F12/02

CPC分类号： G06F13/4068 ,  G06F9/3004 ,  G06F9/3885 ,  G06F13/4282 ,  G06F2213/0026

摘要： An apparatus and a method are disclosed for tracking use of a specialized hardware component in symmetric multiprocessing computing device. A device includes a memory and one or more multi-core processors attached to a coherent memory bus. A proxy for a specialized hardware component (SHC) such as an accelerator, FPGA, or ASIC is placed in communication with the coherent memory bus. The proxy may be attached to another bus such as a peripheral component interconnect express (PCIe) bus. A tracker updates an allocated counting register with counts of events related to use of the SHC. When requested, information from the counting register is provided such as to an external device or client communicating with the multiprocessing computing device. The tracker may follow calls or messages to the SHC. The tracker may accumulate a count of message size or mode of use or use of certain functions of the SHC.

公开(公告)号：US09892060B2

公开(公告)日：2018-02-13

申请号：US14956789

申请日：2015-12-02

申请人： International Business Machines Corporation

发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F12/10 ,  G06F12/1045 ,  G06F12/0808 ,  G06F12/1027 ,  G06F11/263 ,  G06F12/1009 ,  G06F12/0831

CPC分类号： G06F12/1045 ,  G06F11/263 ,  G06F12/0808 ,  G06F12/0833 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/681 ,  G06F2212/683

摘要： A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

公开(公告)号：US20170220442A1

公开(公告)日：2017-08-03

申请号：US15244799

申请日：2016-08-23

申请人： International Business Machines Corporation

发明人： Manoj Dusanapudi ,  Shakti Kapoor

IPC分类号： G06F11/263 ,  G06F11/22

CPC分类号： G06F11/263 ,  G06F3/0617 ,  G06F3/065 ,  G06F3/0683 ,  G06F11/2236 ,  G06F11/2635 ,  G06F12/0806 ,  G06F2212/1024 ,  G06F2212/45 ,  G06F2212/608 ,  G11C29/08 ,  G11C29/10 ,  G11C29/36 ,  G11C29/56004

摘要： Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.