Invention Grant
- Patent Title: Methods of forming package structures for enhanced memory capacity and structures formed thereby
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Application No.: US15392006Application Date: 2016-12-28
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Publication No.: US10177161B2Publication Date: 2019-01-08
- Inventor: Navneet K. Singh , Shanto A. Thomas , Ranjul Balakrishnan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H01L21/332
- IPC: H01L21/332 ; H01L29/66 ; H01L27/11512 ; H01L27/108

Abstract:
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
Public/Granted literature
- US20180182734A1 METHODS OF FORMING PACKAGE STRUCTURES FOR ENHANCED MEMORY CAPACITY AND STRUCTURES FORMED THEREBY Public/Granted day:2018-06-28
Information query
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