公开(公告)号：US10734393B2

公开(公告)日：2020-08-04

申请号：US16182972

申请日：2018-11-07

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L29/66 ,  H01L21/332 ,  H01L27/11512 ,  H01L27/108 ,  H01L25/065 ,  H01L23/00

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.

公开(公告)号：US20190074281A1

公开(公告)日：2019-03-07

申请号：US16182972

申请日：2018-11-07

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L27/11512 ,  H01L27/108 ,  H01L25/065 ,  H01L23/00

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.

公开(公告)号：US10177161B2

公开(公告)日：2019-01-08

申请号：US15392006

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L21/332 ,  H01L29/66 ,  H01L27/11512 ,  H01L27/108

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.

公开(公告)号：US20180182734A1

公开(公告)日：2018-06-28

申请号：US15392006

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L27/11512 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/10897 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.