Invention Grant
- Patent Title: Microelectronic package for wafer-level chip scale packaging with fan-out
-
Application No.: US15332991Application Date: 2016-10-24
-
Publication No.: US10181457B2Publication Date: 2019-01-15
- Inventor: Ashok S. Prabhu , Rajesh Katkar
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L25/10 ; H01L21/48 ; H01L21/56 ; H01L21/60

Abstract:
Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.
Public/Granted literature
- US20170117260A1 Microelectronic Package for Wafer-Level Chip Scale Packaging with Fan-Out Public/Granted day:2017-04-27
Information query
IPC分类: