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公开(公告)号:US10325877B2
公开(公告)日:2019-06-18
申请号:US15959619
申请日:2018-04-23
申请人: Invensas Corporation
IPC分类号: H01L23/00 , H05K1/02 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/16 , H01L23/552 , H01L25/10 , H01L25/00
摘要: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
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公开(公告)号:US10115678B2
公开(公告)日:2018-10-30
申请号:US15804122
申请日:2017-11-06
申请人: Invensas Corporation
发明人: Abiola Awujoola , Zhuowen Sun , Wael Zohni , Ashok S. Prabhu , Willmar Subido
IPC分类号: H01L23/552 , H01L23/00 , H01L25/065 , H01L25/10 , H01L23/498
摘要: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.
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公开(公告)号:US20170194281A1
公开(公告)日:2017-07-06
申请号:US14997774
申请日:2016-01-18
申请人: Invensas Corporation
IPC分类号: H01L23/00 , H01L23/498 , H01L25/065 , H01L23/31 , H01L25/16
CPC分类号: H01L24/49 , H01L23/3121 , H01L23/49838 , H01L23/552 , H01L24/17 , H01L24/48 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/04042 , H01L2224/11334 , H01L2224/16145 , H01L2224/16227 , H01L2224/17051 , H01L2224/32145 , H01L2224/32225 , H01L2224/48108 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49109 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/1023 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H05K1/0284 , H01L2224/45099 , H01L2924/00012 , H01L2924/00
摘要: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
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公开(公告)号:US09666513B2
公开(公告)日:2017-05-30
申请号:US15342744
申请日:2016-11-03
申请人: Invensas Corporation
发明人: Ashok S. Prabhu , Rajesh Katkar , Sean Moran
IPC分类号: H01L23/552 , H01L23/495 , H01L23/29 , H01L23/31 , H01L21/56 , H01L25/10 , H01L25/00 , H01L23/00
CPC分类号: H01L23/49575 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/295 , H01L23/3107 , H01L23/49541 , H01L23/49568 , H01L23/552 , H01L24/24 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/85 , H01L24/96 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/24175 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/49175 , H01L2224/73265 , H01L2224/85005 , H01L2224/97 , H01L2225/1029 , H01L2225/1035 , H01L2225/1064 , H01L2225/107 , H01L2225/1094 , H01L2924/00014 , H01L2924/181 , H01L2924/18162 , H01L2924/18165 , H01L2924/3025 , H01L2924/00012 , H01L2224/85 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/85399
摘要: An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.
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公开(公告)号:US09984992B2
公开(公告)日:2018-05-29
申请号:US14997774
申请日:2016-01-18
申请人: Invensas Corporation
IPC分类号: H05K1/02 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/16
CPC分类号: H01L24/49 , H01L23/3121 , H01L23/49838 , H01L23/552 , H01L24/17 , H01L24/48 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/04042 , H01L2224/11334 , H01L2224/16145 , H01L2224/16227 , H01L2224/17051 , H01L2224/32145 , H01L2224/32225 , H01L2224/48108 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49109 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/1023 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H05K1/0284 , H01L2224/45099 , H01L2924/00012 , H01L2924/00
摘要: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
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公开(公告)号:US20180026019A1
公开(公告)日:2018-01-25
申请号:US15393112
申请日:2016-12-28
申请人: Invensas Corporation
发明人: Min Tao , Hoki Kim , Ashok S. Prabhu , Zhuowen Sun , Wael Zohni , Belgacem Haba
CPC分类号: H01L25/0657 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/52 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/3157 , H01L23/5283 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/09 , H01L24/46 , H01L24/49 , H01L24/83 , H01L25/0652 , H01L25/071 , H01L25/105 , H01L25/112 , H01L25/18 , H01L25/50 , H01L2224/02331 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06548 , H01L2225/06555 , H01L2225/06589 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/19107
摘要: Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.
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公开(公告)号:US20180026017A1
公开(公告)日:2018-01-25
申请号:US15393068
申请日:2016-12-28
申请人: Invensas Corporation
发明人: Min Tao , Hoki Kim , Ashok S. Prabhu , Zhuowen Sun , Wael Zohni , Belgacem Haba
CPC分类号: H01L25/0657 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/52 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/3157 , H01L23/5283 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/09 , H01L24/46 , H01L24/49 , H01L24/83 , H01L25/0652 , H01L25/071 , H01L25/105 , H01L25/112 , H01L25/18 , H01L25/50 , H01L2224/02331 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06548 , H01L2225/06555 , H01L2225/06589 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/19107
摘要: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.
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公开(公告)号:US20180026016A1
公开(公告)日:2018-01-25
申请号:US15393119
申请日:2016-12-28
申请人: Invensas Corporation
发明人: Min Tao , Hoki Kim , Ashok S. Prabhu , Zhuowen Sun , Wael Zohni , Belgacem Haba
CPC分类号: H01L25/0657 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/52 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/3157 , H01L23/5283 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/09 , H01L24/46 , H01L24/49 , H01L24/83 , H01L25/0652 , H01L25/071 , H01L25/105 , H01L25/112 , H01L25/18 , H01L25/50 , H01L2224/02331 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06548 , H01L2225/06555 , H01L2225/06589 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/19107
摘要: Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.
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公开(公告)号:US09825002B2
公开(公告)日:2017-11-21
申请号:US15208985
申请日:2016-07-13
申请人: Invensas Corporation
发明人: Rajesh Katkar , Reynaldo Co , Scott McGrath , Ashok S. Prabhu , Sangil Lee , Liang Wang , Hong Shen
IPC分类号: H01L21/56 , H01L25/065 , H01L25/00 , H01L23/00
CPC分类号: H01L25/0652 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/50 , H01L2224/02335 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/83005 , H01L2224/9222 , H01L2225/06506 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2225/06596 , H01L2924/10252 , H01L2924/10253 , H01L2924/1032 , H01L2924/10329 , H01L2924/1037 , H01L2924/1436 , H01L2924/1438 , H01L2924/18162 , H01L2924/19107 , H01L2224/19
摘要: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.
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公开(公告)号:US09490222B1
公开(公告)日:2016-11-08
申请号:US14880967
申请日:2015-10-12
申请人: Invensas Corporation
发明人: Abiola Awujoola , Zhuowen Sun , Wael Zohni , Ashok S. Prabhu , Willmar Subido
IPC分类号: H01L23/552 , H01L23/00
CPC分类号: H01L23/552 , H01L23/49811 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/04042 , H01L2224/1134 , H01L2224/12105 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/16265 , H01L2224/17051 , H01L2224/17181 , H01L2224/215 , H01L2224/2919 , H01L2224/32225 , H01L2224/45015 , H01L2224/48105 , H01L2224/48227 , H01L2224/48472 , H01L2224/4942 , H01L2224/73204 , H01L2224/73207 , H01L2224/73227 , H01L2224/73253 , H01L2224/73259 , H01L2224/73265 , H01L2224/73267 , H01L2224/85444 , H01L2224/85455 , H01L2225/06513 , H01L2225/06517 , H01L2225/1023 , H01L2225/1052 , H01L2924/00014 , H01L2924/01322 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H01L2224/45099 , H01L2924/2075 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/05599
摘要: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.
摘要翻译: 公开了一般涉及具有防止干扰的微电子封装的装置。 在其装置中,基板具有与上表面相对的上表面和下表面,并具有接地平面。 第一微电子器件耦合到衬底的上表面。 引线接合线耦合到接地平面,用于对其进行干涉并延伸离开衬底的上表面。 引线接合线的第一部分被定位成相对于干涉为第一微电子器件提供屏蔽区域。 导线接合线的第二部分不定位成提供屏蔽区域。 第二微电子器件耦合到衬底并且位于屏蔽区域外部。 导电表面在用于覆盖屏蔽区域的引线接合线的第一部分之上。
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