A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions.