公开(公告)号：US09971605B2

公开(公告)日：2018-05-15

申请号：US14281709

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/44 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.

公开(公告)号：US09535488B2

公开(公告)日：2017-01-03

申请号：US14281729

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F13/00 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F9/38 ,  G06F9/30 ,  G06F1/04 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.

Abstract translation: 微处理器包括指示器和多个处理核心。 多个处理核心中的每一个被配置为对指示器进行采样。 当指示符指示第一预定值时，多个处理核心被配置为将多个处理核心中的默认处理核心共同指定为自举处理器。 当指示符指示与第一预定值不同的第二预定值时，多个处理核被配置为将默认处理核以外的多个处理核中的一个统一指定为引导处理器。

公开(公告)号：US09395802B2

公开(公告)日：2016-07-19

申请号：US14285448

申请日：2014-05-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain ,  Stephan Gaskins

IPC: G06F1/32 ,  G06F12/12 ,  G06F12/08 ,  G06F11/10 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  G11C29/44

CPC classification number: G06F3/0631 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/12 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/601 ,  G06F2212/608 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/787 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract translation: 一种装置包括熔丝阵列和商店。 保险丝阵列用多个核心的压缩配置数据编程。 存储器耦合到多个核心，并且包括多个子存储器，每个子存储器对应于多个核心中的每一个，多个核心中的一个核心在上电/复位时访问半导体熔丝阵列以读取，以及 对压缩的配置数据进行解压缩，并且在多个子存储器中的多个核心的每个内存储一个或多个高速缓存存储器的多个解压配置数据集。 多个核心中的每一个具有睡眠逻辑。 睡眠逻辑被配置为随后访问多个子商店中的每一个的对应的一个，以检索并使用解压配置数据集来初始化电源门控事件之后的一个或多个高速缓存。

公开(公告)号：US20150067666A1

公开(公告)日：2015-03-05

申请号：US14281786

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/445

CPC classification number: G06F8/665 ,  G06F8/654 ,  G06F8/656 ,  G06F8/67 ,  G06F9/268 ,  G06F9/328 ,  G06F11/366 ,  Y02B60/183 ,  Y02D10/42

Abstract: A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.

Abstract translation: 微处理器包括多个处理核心，其中多个处理核心中的每一个执行微代码并且包括用于修补微代码的硬件。 多个处理核心的第一核心被配置为遇到指示第一核心应用微代码补丁的指令。 多个处理核心的第一核心还被配置为响应于遇到该指令，通知微代码补丁的多个处理核心中的另一个的每个核心，并将微代码补丁应用于第一核心的硬件。 多个第一核心以外的多个处理核心的每个核心被配置为响应于第一核心被通知而将微码补丁应用于核心的硬件。

公开(公告)号：US20150067219A1

公开(公告)日：2015-03-05

申请号：US14281729

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/38 ,  G06F13/24

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.

Abstract translation: 微处理器包括指示器和多个处理核心。 多个处理核心中的每一个被配置为对指示器进行采样。 当指示符指示第一预定值时，多个处理核心被配置为将多个处理核心中的默认处理核心共同指定为自举处理器。 当指示符指示与第一预定值不同的第二预定值时，多个处理核被配置为将默认处理核以外的多个处理核中的一个统一指定为引导处理器。

公开(公告)号：US10108431B2

公开(公告)日：2018-10-23

申请号：US15265127

申请日：2016-09-14

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Stephan Gaskins

IPC: G06F1/00 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/4401 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

公开(公告)号：US09891928B2

公开(公告)日：2018-02-13

申请号：US15232506

申请日：2016-08-09

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F15/76 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

公开(公告)号：US09891927B2

公开(公告)日：2018-02-13

申请号：US14281551

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Stephan Gaskins

IPC: G06F1/00 ,  H04L29/06 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

公开(公告)号：US09471133B2

公开(公告)日：2016-10-18

申请号：US14281758

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F12/08 ,  G06F1/32 ,  G06F1/04 ,  G06F1/12 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F13/24

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.

Abstract translation: 微处理器包括多个处理核心，服务处理单元和可由服务处理单元和多个处理核心访问的存储器。 多个处理核心中的至少一个被配置为将补丁写入存储器。 所述补丁包括要从所述存储器中取出并由所述服务处理单元在由所述多个处理核心中的至少一个写入所述存储器之后执行的一个或多个指令。

公开(公告)号：US20150212947A1

公开(公告)日：2015-07-30

申请号：US14188905

申请日：2014-02-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0891 ,  G06F1/3203 ,  G06F1/3215 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/0893 ,  G06F2212/6082 ,  Y02D10/152 ,  Y02D50/20

Abstract: A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions.

Abstract translation: 微处理器包括高速缓冲存储器和控制模块。 控制模块使高速缓存大小为零，随后将其设置在零和高速缓存的完整大小之间，在将大小从零到满之后，从高速缓存中计数一些驱逐，并且当驱逐次数达到预定时增加大小 驱逐次数 或者，微处理器包括：多个核，每个具有第一高速缓冲存储器; 由核心共享的第二缓存存储器; 和控制模块。 控制模块将所有内核置于休眠状态，并使第二个缓存大小为零，并接收一个命令以唤醒其中一个内核。 控制模块在接收到命令之后对来自唤醒的核心的第一高速缓存进行计数，并且当驱逐次数达到预定的驱逐次数时使第二高速缓存大小不为零。