Invention Grant
- Patent Title: Multilayer wiring substrate
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Application No.: US15944626Application Date: 2018-04-03
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Publication No.: US10237973B2Publication Date: 2019-03-19
- Inventor: Takashi Tokoro
- Applicant: CANON KABUSHIKI KAISHA
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Canon U.S.A., Inc. IP Division
- Priority: JP2017-077271 20170410
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/02 ; H05K3/42 ; H01R13/6471 ; H05K3/46 ; H05K3/34

Abstract:
Signal transmission characteristics in a case where a conductive pin is inserted into a through hole to perform connection with an external circuit are improved. A multilayer wiring substrate includes a front layer and a rear layer, and includes a plurality of layers in an inner layer. A conductive portion is provided in each of the layers, and a wiring is disposed on the rear layer. The conductive pin for connection with the external circuit is inserted into the through hole. A land is disposed around the through hole on the rear layer, and the land and the conductive pin are connected to each other through solder.
Public/Granted literature
- US20180295721A1 MULTILAYER WIRING SUBSTRATE Public/Granted day:2018-10-11
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