An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory that includes multiple memory cells arranged in multiple planes that each includes one or more blocks of the memory cells. The storage circuitry is configured to apply a multi-plane storage operation to multiple blocks simultaneously across the respective planes. In response to detecting that the multi-plane storage operation has failed, the storage circuitry is configured to apply a single-plane storage operation to one or more of the blocks that were accessed in the multi-plane storage operation, including a given block, and to identify the given block as a bad block if the single-plane operation applied to the given block fails. The storage circuitry is further configured to store data in the blocks that were accessed in the multi-plane operation but were not identified as bad blocks.