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公开(公告)号：US20180203774A1
公开(公告)日：2018-07-19
申请号：US15409583
申请日：2017-01-19
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
CPC classification number: G06F11/2094 , G06F2201/805 , G06F2201/82 , G06F2201/85 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2216/14
Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory that includes multiple memory cells arranged in multiple planes that each includes one or more blocks of the memory cells. The storage circuitry is configured to apply a multi-plane storage operation to multiple blocks simultaneously across the respective planes. In response to detecting that the multi-plane storage operation has failed, the storage circuitry is configured to apply a single-plane storage operation to one or more of the blocks that were accessed in the multi-plane storage operation, including a given block, and to identify the given block as a bad block if the single-plane operation applied to the given block fails. The storage circuitry is further configured to store data in the blocks that were accessed in the multi-plane operation but were not identified as bad blocks.
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公开(公告)号：US20170177265A1
公开(公告)日：2017-06-22
申请号：US14975789
申请日：2015-12-20
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
CPC classification number: G06F3/0638 , G06F3/0604 , G06F3/0629 , G06F3/0679 , G11C11/5628 , G11C11/5642 , G11C16/3436 , G11C2211/5621 , G11C2211/5641 , G11C2211/5648
Abstract: A method for data storage includes preparing first data having a first size for storage in a memory device that stores data having a nominal size larger than the first size, by programming a group of memory cells to multiple predefined levels using a one-pass program-and-verify scheme. The first data is combined with dummy data to produce first combined data having the nominal size, and is sent to the memory device for storage in the group. The dummy data is chosen to limit the levels to which the memory cells in the group are programmed to a partial subset of the predefined levels. In response to identifying second data to be stored in the group, the second data is combined with the first data to obtain second combined data having the nominal size, and is sent to the memory device for storage, in place, in the group.
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公开(公告)号：US10353769B2
公开(公告)日：2019-07-16
申请号：US15658433
申请日：2017-07-25
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
Abstract: A storage system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells coupled to multiple Bit Lines (BLs). The memory cells are programmed and read in sub-groups of multiple BLs, and the sub-groups correspond to respective addresses. The storage circuitry is configured to generate a sequence of addresses for reading memory cells that together store a data part and a pattern part containing a predefined pattern, via multiple respective sub-groups, to detect that the data part read from the memory cells is erroneous due to a fault that occurred in the sequence of addresses by identifying a mismatch between the pattern part read from the memory cells and the predefined pattern, and, in response to detecting the fault, to take a corrective measure to recover an error-free version of the data part.
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公开(公告)号：US20180032276A1
公开(公告)日：2018-02-01
申请号：US15728518
申请日：2017-10-10
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
CPC classification number: G06F3/0638 , G06F3/0604 , G06F3/0629 , G06F3/0679 , G11C11/5628 , G11C11/5642 , G11C16/3436 , G11C2211/5621 , G11C2211/5641 , G11C2211/5648
Abstract: A method for data storage includes preparing first data having a first size for storage in a memory device that stores data having a nominal size larger than the first size, by programming a group of memory cells to multiple predefined levels using a one-pass program-and-verify scheme. The first data is combined with dummy data to produce first combined data having the nominal size, and is sent to the memory device for storage in the group. The dummy data is chosen to limit the levels to which the memory cells in the group are programmed to a partial subset of the predefined levels. In response to identifying second data to be stored in the group, the second data is combined with the first data to obtain second combined data having the nominal size, and is sent to the memory device for storage, in place, in the group.
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5.发明授权公开(公告)号：US09811284B2
公开(公告)日：2017-11-07
申请号：US14975789
申请日：2015-12-20
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
CPC classification number: G06F3/0638 , G06F3/0604 , G06F3/0629 , G06F3/0679 , G11C11/5628 , G11C11/5642 , G11C16/3436 , G11C2211/5621 , G11C2211/5641 , G11C2211/5648
Abstract: A method for data storage includes preparing first data having a first size for storage in a memory device that stores data having a nominal size larger than the first size, by programming a group of memory cells to multiple predefined levels using a one-pass program-and-verify scheme. The first data is combined with dummy data to produce first combined data having the nominal size, and is sent to the memory device for storage in the group. The dummy data is chosen to limit the levels to which the memory cells in the group are programmed to a partial subset of the predefined levels. In response to identifying second data to be stored in the group, the second data is combined with the first data to obtain second combined data having the nominal size, and is sent to the memory device for storage, in place, in the group.
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Patent Agency Ranking
公开(公告)号：US09529663B1
公开(公告)日：2016-12-27
申请号：US14975784
申请日：2015-12-20
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
CPC classification number: G11C16/3445 , G11C16/349 , G11C29/025 , G11C29/4401 , G11C2029/0409
Abstract: A method includes, in a memory block, which includes at least a string of memory cells that is selectable using at least a select transistor, sensing a current flowing through the string. A failure in the memory block, which causes the string to conduct even when unselected using the select transistor, is detected based on the sensed current. A corrective action is initiated in response to the identified failure.
Abstract translation: 一种方法包括在存储器块中，其包括可使用至少一个选择晶体管选择的至少一串存储器单元，感测流过该串的电流。 基于感测到的电流来检测存储器块中的故障，即使用选择晶体管在未选择时也导致串导通。 响应于所识别的故障启动纠正措施。
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公开(公告)号：US20190034273A1
公开(公告)日：2019-01-31
申请号：US15658433
申请日：2017-07-25
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
CPC classification number: G06F11/1016 , G06F11/08 , G06F11/1076 , G06F11/1441 , G06F2201/805 , G06F2201/82
Abstract: A storage system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells coupled to multiple Bit Lines (BLs). The memory cells are programmed and read in sub-groups of multiple BLs, and the sub-groups correspond to respective addresses. The storage circuitry is configured to generate a sequence of addresses for reading memory cells that together store a data part and a pattern part containing a predefined pattern, via multiple respective sub-groups, to detect that the data part read from the memory cells is erroneous due to a fault that occurred in the sequence of addresses by identifying a mismatch between the pattern part read from the memory cells and the predefined pattern, and, in response to detecting the fault, to take a corrective measure to recover an error-free version of the data part.
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8.发明授权公开(公告)号：US10191683B2
公开(公告)日：2019-01-29
申请号：US15728518
申请日：2017-10-10
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
Abstract: A method for data storage includes preparing first data having a first size for storage in a memory device that stores data having a nominal size larger than the first size, by programming a group of memory cells to multiple predefined levels using a one-pass program-and-verify scheme. The first data is combined with dummy data to produce first combined data having the nominal size, and is sent to the memory device for storage in the group. The dummy data is chosen to limit the levels to which the memory cells in the group are programmed to a partial subset of the predefined levels. In response to identifying second data to be stored in the group, the second data is combined with the first data to obtain second combined data having the nominal size, and is sent to the memory device for storage, in place, in the group.
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公开(公告)号：US20180121131A1
公开(公告)日：2018-05-03
申请号：US15854299
申请日：2017-12-26
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Charan Srinivasan , Matthew J. Byom
IPC: G06F3/06
CPC classification number: G06F3/0647 , G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: Systems and methods for managing data in non-volatile memory devices across a large range of operating temperatures are provided. Embodiments discussed herein selectively reprogram previously programmed data at a temperature that better enables the data to be read regardless of where within the range of operating temperatures the data is being read. Circuitry and methods discussed herein can keep track of a program temperature associated with each portion of non-volatile memory and use this information along with other criteria to selectively perform temperature based moves of data. This enables a mechanism for data to programmed in out-of-bounds temperature ranges to be reprogrammed within an in-bounds temperatures range so that a temperature delta between the reprogrammed temperature and the read operation temperature is below a threshold that ensure efficient and error free read operations to be performed.
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公开(公告)号：US10248515B2
公开(公告)日：2019-04-02
申请号：US15409583
申请日：2017-01-19
Applicant: Apple Inc.
Inventor： Charan Srinivasan , Eyal Gurgi
Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory that includes multiple memory cells arranged in multiple planes that each includes one or more blocks of the memory cells. The storage circuitry is configured to apply a multi-plane storage operation to multiple blocks simultaneously across the respective planes. In response to detecting that the multi-plane storage operation has failed, the storage circuitry is configured to apply a single-plane storage operation to one or more of the blocks that were accessed in the multi-plane storage operation, including a given block, and to identify the given block as a bad block if the single-plane operation applied to the given block fails. The storage circuitry is further configured to store data in the blocks that were accessed in the multi-plane operation but were not identified as bad blocks.
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