Invention Grant
- Patent Title: Semiconductor device layout and method for forming same
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Application No.: US15596977Application Date: 2017-05-16
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Publication No.: US10269951B2Publication Date: 2019-04-23
- Inventor: Peter Almern Losee , Alexander Bolotnikov , Stacey Joy Kennerly , James William Kretchmer
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: GENERAL ELECTRIC COMPANY
- Current Assignee: GENERAL ELECTRIC COMPANY
- Current Assignee Address: US NY Schenectady
- Agency: GE Global Patent Operation
- Agent John P. Darling
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/36 ; H01L29/16 ; H01L29/20 ; H01L21/265 ; H01L21/266 ; H01L29/78 ; H01L29/10 ; H01L29/08
Abstract:
A semiconductor device is provided. The semiconductor device includes a semiconductor device layer having silicon carbide and having an upper surface and a lower surface. The semiconductor device also includes a heavily doped body region formed in the upper surface of the semiconductor device layer. The semiconductor device further includes a gate stack formed adjacent to and on top of the upper surface of the semiconductor device layer, wherein the gate stack is not formed adjacent to the heavily doped body region.
Public/Granted literature
- US20180337273A1 SEMICONDUCTOR DEVICE LAYOUT AND METHOD FOR FORMING SAME Public/Granted day:2018-11-22
Information query
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