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公开(公告)号：US10957759B2
公开(公告)日：2021-03-23
申请号：US16235486
申请日：2018-12-28
发明人： Stephen Daley Arthur , Reza Ghandi , Alexander Viktorovich Bolotnikov , David Alan Lilienfeld , Peter Almern Losee
摘要： A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.
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公开(公告)号：US10955297B2
公开(公告)日：2021-03-23
申请号：US16002769
申请日：2018-06-07
摘要： A system for monitoring a junction temperature of a semiconductor device includes a sensing resistor electrically coupled to a source terminal of the semiconductor device in a gate loop of the semiconductor device. The system includes a detection circuit electrically coupled to the gate loop of the semiconductor device and configured to measure a voltage difference across the sensing resistor. The system also includes an electronic control unit electrically coupled to the gate loop and the detection circuit. The electronic control unit is configured to determine a first gate current peak during a switching process of the semiconductor device, wherein the first gate current peak is determined based on the voltage detected by the detection circuit. The electronic control unit is configured to determine the junction temperature based on the first gate current peak.
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公开(公告)号：US20190245035A1
公开(公告)日：2019-08-08
申请号：US15890077
申请日：2018-02-06
IPC分类号： H01L29/06 , H01L29/16 , H01L21/02 , H01L21/761 , H01L21/265 , H01L21/324 , H01L27/088 , H01L27/092
CPC分类号： H01L29/0646 , H01L21/02529 , H01L21/26506 , H01L21/324 , H01L21/761 , H01L27/088 , H01L27/092 , H01L29/1608
摘要： An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).
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公开(公告)号：US20190140048A1
公开(公告)日：2019-05-09
申请号：US16010531
申请日：2018-06-18
IPC分类号： H01L29/06 , H01L21/04 , H01L29/20 , H01L21/266 , H01L29/78 , H01L21/265 , H01L29/16
摘要： The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.
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公开(公告)号：US10243039B2
公开(公告)日：2019-03-26
申请号：US15077579
申请日：2016-03-22
IPC分类号： H01L21/04 , H01L29/06 , H01L29/16 , H01L29/66 , H01L29/73 , H01L29/78 , H01L29/732 , H01L29/808 , H01L29/861 , H01L29/872
摘要： A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.
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公开(公告)号：US20180166531A1
公开(公告)日：2018-06-14
申请号：US15379214
申请日：2016-12-14
IPC分类号： H01L29/06 , H01L29/36 , H01L29/16 , H01L29/20 , H01L21/265 , H01L21/266
CPC分类号： H01L29/0634 , H01L21/26506 , H01L21/266 , H01L29/1608 , H01L29/2003 , H01L29/36
摘要： The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.
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公开(公告)号：US09997507B2
公开(公告)日：2018-06-12
申请号：US13950736
申请日：2013-07-25
IPC分类号： H01L29/76 , H01L21/8252 , H01L21/8258 , H01L27/02
CPC分类号： H01L27/0248 , H01L2924/0002
摘要： A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.
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公开(公告)号：US20170345890A1
公开(公告)日：2017-11-30
申请号：US15164928
申请日：2016-05-26
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0619 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L29/7832 , H01L29/872
摘要： Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.
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公开(公告)号：US11233157B2
公开(公告)日：2022-01-25
申请号：US16147210
申请日：2018-09-28
发明人： Stephen Daley Arthur , Alexander Viktorovich Bolotnikov , Reza Ghandi , David Alan Lilienfeld , Peter Almern Losee
IPC分类号： H01L29/812 , H01L29/80 , H01L21/04 , H01L29/66 , H01L29/16
摘要： A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.
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公开(公告)号：US10937870B2
公开(公告)日：2021-03-02
申请号：US16789164
申请日：2020-02-12
IPC分类号： H01L29/16 , H01L29/66 , H01L29/78 , H01L21/04 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/745 , H01L29/74
摘要： The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).
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