- Patent Title: Multiple patterning decomposition and manufacturing methods for IC
-
Application No.: US15689244Application Date: 2017-08-29
-
Publication No.: US10274829B2Publication Date: 2019-04-30
- Inventor: Ken-Hsien Hsieh , Wen-Li Cheng , Pai-Wei Wang , Ru-Gun Liu , Chih-Ming Lai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G03F7/20
- IPC: G03F7/20 ; G06F17/50 ; G03F1/22 ; G03F1/36 ; G03F1/68 ; G03F1/70

Abstract:
A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.
Public/Granted literature
- US20180164695A1 MULTIPLE PATTERNING DECOMPOSITION AND MANUFACTURING METHODS FOR IC Public/Granted day:2018-06-14
Information query
IPC分类: