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公开(公告)号：US10817635B2
公开(公告)日：2020-10-27
申请号：US16133110
申请日：2018-09-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Chih-Ming Lai , Ru-Gun Liu , Wen-Chun Huang , Wen-Li Cheng , Pai-Wei Wang
IPC: G06F30/39 , G03F1/36 , G03F1/70 , G06F119/18 , H01L27/02
Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.
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公开(公告)号：US10276394B2
公开(公告)日：2019-04-30
申请号：US15704367
申请日：2017-09-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Wen-Li Cheng , Dong-Yo Jheng , Chih-Ming Lai , Ru-Gun Liu
IPC: G06F7/50 , H01L21/308 , G06F17/50
Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.
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公开(公告)号：US20170316938A1
公开(公告)日：2017-11-02
申请号：US15267341
申请日：2016-09-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Ping Chiang , Ya-Ting Chang , Wen-Li Cheng , Nian-Fuh Cheng , Ming-Hui Chih , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau
IPC: H01L21/033 , G03F7/20
CPC classification number: G03F7/70283 , G03F1/70 , G06F17/5081 , H01L21/0338 , H01L21/31144 , H01L21/76831 , H01L21/76843 , H01L31/1892
Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.
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公开(公告)号：US20190252200A1
公开(公告)日：2019-08-15
申请号：US16393339
申请日：2019-04-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Wen-Li Cheng , Dong-Yo Jheng , Chih-Ming Lai , Ru-Gun Liu
IPC: H01L21/308 , G06F17/50
CPC classification number: H01L21/3088 , G03F1/70 , G03F7/70425 , G06F17/5068 , G06F17/5081 , G06F2217/12
Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.
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公开(公告)号：US10274829B2
公开(公告)日：2019-04-30
申请号：US15689244
申请日：2017-08-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Wen-Li Cheng , Pai-Wei Wang , Ru-Gun Liu , Chih-Ming Lai
Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.
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Patent Agency Ranking
公开(公告)号：US20170193147A1
公开(公告)日：2017-07-06
申请号：US15179754
申请日：2016-06-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Chih-Ming Lai , Ru-Gun Liu , Wen-Chun Huang , Wen-Li Cheng , Pai-Wei Wan
CPC classification number: G06F17/5068 , G03F1/36 , G03F1/70 , G06F2217/12
Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.
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公开(公告)号：US20200083058A1
公开(公告)日：2020-03-12
申请号：US16682963
申请日：2019-11-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Wen-Li Cheng , Dong-Yo Jheng , Chih-Ming Lai , Ru-Gun Liu
IPC: H01L21/308 , G06F17/50 , G03F1/70 , G03F7/20
Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.
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公开(公告)号：US10509881B2
公开(公告)日：2019-12-17
申请号：US15718522
申请日：2017-09-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Ping Chiang , Ming-Hui Chih , Chih-Wei Hsu , Ping-Chieh Wu , Ya-Ting Chang , Tsung-Yu Wang , Wen-Li Cheng , Hui En Yin , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau
Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
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公开(公告)号：US10078718B2
公开(公告)日：2018-09-18
申请号：US15179754
申请日：2016-06-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Chih-Ming Lai , Ru-Gun Liu , Wen-Chun Huang , Wen-Li Cheng , Pai-Wei Wan
Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.
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公开(公告)号：US10770304B2
公开(公告)日：2020-09-08
申请号：US16682963
申请日：2019-11-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ken-Hsien Hsieh , Wen-Li Cheng , Dong-Yo Jheng , Chih-Ming Lai , Ru-Gun Liu
IPC: G06F17/50 , H01L21/308 , G03F7/20 , G03F1/70 , G06F30/39 , G06F30/398 , G06F119/18
Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.
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