Invention Grant
- Patent Title: Loading effect reduction through multiple coat-etch processes
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Application No.: US15642559Application Date: 2017-07-06
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Publication No.: US10276392B2Publication Date: 2019-04-30
- Inventor: Jin-Dah Chen , Ming-Feng Shieh , Han-Wei Wu , Yu-Hsien Lin , Po-Chun Liu , Stan Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L21/283 ; H01L21/308 ; H01L21/8234 ; H01L29/49 ; H01L29/66 ; H01L29/78 ; H01L29/51
Abstract:
First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
Public/Granted literature
- US20170309718A1 LOADING EFFECT REDUCTION THROUGH MULTIPLE COAT-ETCH PROCESSES Public/Granted day:2017-10-26
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