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    Loading effect reduction through multiple coat-etch processes
    1.
    发明授权
    Loading effect reduction through multiple coat-etch processes 有权

    公开(公告)号：US10755936B2

    公开(公告)日：2020-08-25

    申请号：US16396429

    申请日：2019-04-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

    IPC: H01L21/306 ,  H01L21/283 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

    High electron mobility transistors
    4.
    发明授权
    High electron mobility transistors 有权

    公开(公告)号：US10109729B2

    公开(公告)日：2018-10-23

    申请号：US15242653

    申请日：2016-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/338 ,  H01L29/778 ,  H01L29/43 ,  H01L29/20 ,  H01L29/205 ,  H01L29/201

    Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

    HIGH ELECTRON MOBILITY TRANSISTORS
    6.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTORS 审中-公开
    高电子移动晶体管

    公开(公告)号：US20160359034A1

    公开(公告)日：2016-12-08

    申请号：US15242653

    申请日：2016-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

    Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

    Abstract translation: 本公开涉及具有施主双层的晶体管器件，其被配置为在源极和漏极触点内提供低电阻，同时保持沟道层内的高迁移率二维电子气以及相关的形成方法。 在一些实施例中，晶体管器件具有设置在衬底上的沟道层和设置在沟道层上的施主双层。 施主双层包括设置在沟道层上并具有第一范围内的第一摩尔分数z的AlzGa（1-z）N的迁移率增强层，以及Al x Ga（1-x）N的电阻减小层 设置在AlzGa（1-z）N的迁移率增强层上并与之接触，并且在小于第一范围的第二范围内具有第二摩尔分数x。 源极和漏极接触在Al x Ga（1-x）N的电阻减少层之上。 供体双层具有从施主双层的顶表面到底表面单调减小的导带能量。

    High electron mobility transistors
    7.
    发明授权
    High electron mobility transistors 有权
    高电子迁移率晶体管

    公开(公告)号：US09425276B2

    公开(公告)日：2016-08-23

    申请号：US13745925

    申请日：2013-01-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/338 ,  H01L29/43 ,  H01L29/778 ,  H01L29/20 ,  H01L29/201

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

    Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

    Abstract translation: 本公开涉及双层AlGaN的施主层和在高电子迁移率晶体管（HEMT）内的相关制造方法，其被配置为提供低电阻欧姆源极和漏极触点以降低功耗，同时保持高的迁移率 在HEMT的通道内的二维电子气（2DEG）。 双层AlGaN的施主层包括位于迁移率增强层上的Al x Ga（1-x）N的电阻减小层AlzGa（1-z）N的迁移率增强层，其中欧姆源和漏极 触点连接到HEMT。 移动性增强层下方设置沟道层，其中2DEG驻留，形成HEMT的沟道。

    High Electron Mobility Transistors
    8.
    发明申请
    High Electron Mobility Transistors 有权
    高电子迁移率晶体管

    公开(公告)号：US20140203289A1

    公开(公告)日：2014-07-24

    申请号：US13745925

    申请日：2013-01-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/66

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

    Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

    Abstract translation: 本公开涉及双层AlGaN的施主层和在高电子迁移率晶体管（HEMT）内的相关制造方法，其被配置为提供低电阻欧姆源极和漏极触点以降低功耗，同时保持高的迁移率 在HEMT的通道内的二维电子气（2DEG）。 双层AlGaN的施主层包括位于迁移率增强层上的Al x Ga（1-x）N的电阻减小层AlzGa（1-z）N的迁移率增强层，其中欧姆源和漏极 触点连接到HEMT。 移动性增强层下方设置沟道层，其中2DEG驻留，形成HEMT的沟道。

    Source/drains in semiconductor devices and methods of forming thereof
    9.
    发明授权
    Source/drains in semiconductor devices and methods of forming thereof 有权

    公开(公告)号：US11824099B2

    公开(公告)日：2023-11-21

    申请号：US16901512

    申请日：2020-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/788

    CPC classification number: H01L29/42384 ,  H01L29/785 ,  H01L29/7889

    Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

    Capping structure to reduce dark current in image sensors
    10.
    发明授权
    Capping structure to reduce dark current in image sensors 有权

    公开(公告)号：US11824077B2

    公开(公告)日：2023-11-21

    申请号：US16952384

    申请日：2020-11-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

    IPC: H01L27/146

    CPC classification number: H01L27/14643 ,  H01L27/14636 ,  H01L27/14685

    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

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