Invention Grant
- Patent Title: Semiconductor package and manufacturing process thereof
-
Application No.: US15147910Application Date: 2016-05-06
-
Publication No.: US10276402B2Publication Date: 2019-04-30
- Inventor: Yu-Feng Chen , Chih-Hua Chen , Chen-Hua Yu , Chung-Shi Liu , Hung-Jui Kuo , Hui-Jung Tsai , Hao-Yi Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L25/065 ; H01L25/00 ; H01L23/538 ; H01L21/56 ; H01L23/31 ; H01L23/00

Abstract:
A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
Public/Granted literature
- US20170271248A1 SEMICONDCUTOR PACKAGE AND MANUFACTURING PROCESS THEREOF Public/Granted day:2017-09-21
Information query
IPC分类: