Invention Grant
- Patent Title: Read-with overridable-invalidate transaction
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Application No.: US15427320Application Date: 2017-02-08
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Publication No.: US10282297B2Publication Date: 2019-05-07
- Inventor: Phanindra Kumar Mannava , Bruce James Mathewson , Jamshed Jalal , Mark David Werkheiser
- Applicant: ARM Limited
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0831 ; G06F12/0804 ; G06F12/0808 ; G06F12/0811 ; G06F12/084 ; G06F12/0842 ; G06F12/0891 ; G06F12/0897

Abstract:
A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.
Public/Granted literature
- US20180225209A1 READ-WITH OVERRIDABLE-INVALIDATE TRANSACTION Public/Granted day:2018-08-09
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