公开(公告)号：US20240273026A1

公开(公告)日：2024-08-15

申请号：US18109454

申请日：2023-02-14

Applicant: Arm Limited

Inventor： Devi Sravanthi Yalamarthy ,  Jamshed Jalal ,  Mark David Werkheiser ,  Wenxuan Zhang ,  Ritukar Khanna ,  Rajani Pai ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0891

Abstract: A data processing apparatus includes one or more cache configuration data stores, a coherence manager, and a shared cache. The coherence manager is configured to track and maintain coherency of cache lines accessed by local caching agents and one or more remote caching agents. The cache lines include local cache lines accessed from a local memory region and remote cache lines accessed from a remote memory region. The shared cache is configured to store local cache lines in a first partition and to store remote cache lines in a second partition. The sizes of the first and second partitions are determined based on values in the one or more cache configuration data stores and may or not overlap. The cache configuration data stores may be programmable by a user or dynamically programmed in response to local memory and remote memory access patterns.

公开(公告)号：US10761987B2

公开(公告)日：2020-09-01

申请号：US16202171

申请日：2018-11-28

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser ,  Michael Filippo ,  Klas Magnus Bruce ,  Paul Gilbert Meyer

IPC: G06F12/0815 ,  G06F13/16

Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.

公开(公告)号：US10657055B1

公开(公告)日：2020-05-19

申请号：US16218962

申请日：2018-12-13

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser ,  Gurunath Ramagiri ,  Mukesh Patel

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0804 ,  G06F12/0817

Abstract: An apparatus and method are provided for managing snoop operations. The apparatus has an interface for receiving access requests from any of N master devices that have associated cache storage, each access request specifying a memory address within memory associated with the apparatus. Snoop filter storage is provided that has a plurality of snoop filter entries, where each snoop filter entry identifies a memory portion and snoop control information indicative of the master devices that have accessed that memory portion. When an access request received at the interface specifies a memory address that is within the memory portion associated with a snoop filter entry, snoop control circuitry uses the snoop control information in that snoop filter entry to determine which master devices to subject to a snoop operation. The snoop control circuitry maintains master indication data used to identify a first subset of the plurality of master devices whose accesses to the memory are to be precisely tracked within the snoop filter storage. The first subset comprises up to M master devices, where M is less than N. Each snoop filter entry has a precise tracking field and an imprecise tracking field. When multiple master devices have accessed the memory portion associated with a snoop filter entry, then the precise tracking field is used to precisely identify each master device of those multiple master devices that is within the first subset. When the multiple master devices includes at least one master device that is not in the first subset, then a generic indication is set in the imprecise tracking field.

公开(公告)号：US10157133B2

公开(公告)日：2018-12-18

申请号：US14965131

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0831

Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

公开(公告)号：US11593025B2

公开(公告)日：2023-02-28

申请号：US16743409

申请日：2020-01-15

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P Ringe ,  Klas Magnus Bruce ,  Ritukar Khanna

IPC: G06F3/06

Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

公开(公告)号：US11550720B2

公开(公告)日：2023-01-10

申请号：US17102997

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P Ringe ,  Mukesh Patel ,  Sakshi Verma

IPC: G06F12/0815 ,  G06F12/0831

Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.

公开(公告)号：US11531620B2

公开(公告)日：2022-12-20

申请号：US17212804

申请日：2021-03-25

Applicant: Arm Limited

Inventor： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

IPC: G06F12/0815 ,  G06F12/0831 ,  G06F13/40

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

公开(公告)号：US11188377B2

公开(公告)日：2021-11-30

申请号：US16592979

申请日：2019-10-04

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser ,  Phanindra Kumar Mannava ,  Bruce James Mathewson

IPC: G06F12/0891 ,  G06F12/0808 ,  G06F9/46 ,  G06F9/455 ,  G06F13/40 ,  G06F12/10 ,  G06F9/38

Abstract: Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.

公开(公告)号：US10452575B1

公开(公告)日：2019-10-22

申请号：US16055211

申请日：2018-08-06

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Mark David Werkheiser ,  Glenn Allan Canto ,  Ashok Kumar Tummala ,  Devi Sravanthi Yalamarthy

IPC: G06F3/00 ,  G06F13/16 ,  G06F3/06

Abstract: A system, apparatus and method for ordering a sequence of processing transactions for a plurality of peripheral units. The sequence of transactions is accomplished by mapping an incoming address to a target endpoint. The ordering of the transactions is agnostic to the type of endpoint being targeted and only considers an identifier of the transaction for ordering purposes.

公开(公告)号：US09507716B2

公开(公告)日：2016-11-29

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Jamshed Jalal ,  Mark David Werkheiser ,  Arthur Laughton ,  George Robert Scott Lloyd ,  Peter Andrew Riocreux ,  Daniel Sara

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。