公开(公告)号：US11573918B1

公开(公告)日：2023-02-07

申请号：US17380112

申请日：2021-07-20

Applicant: Arm Limited

Inventor： Mark David Werkheiser ,  Sai Kumar Marri ,  Lauren Elise Guckert ,  Gurunath Ramagiri ,  Jamshed Jalal

IPC: G06F13/14 ,  G06F13/40

Abstract: Aspects of the present disclosure relate to an interconnect comprising interfaces to communicate with respective requester and receiver node devices, and home nodes. Each home node is configured to: receive requests from one or more requester nodes, each request comprising a target address corresponding to a target receiver nodes; and transmit each said request to the corresponding target receiver node. Mapping circuitry is configured to: associate each of said plurality of home nodes with a given home node cluster; perform a first hashing of the target address of a given request, to determine a target cluster; perform a second hashing of the target address, to determine a target home node within said target cluster; and direct the given message, to the target home node.

公开(公告)号：US11537543B2

公开(公告)日：2022-12-27

申请号：US17189781

申请日：2021-03-02

Applicant: Arm Limited

Inventor： Ashok Kumar Tummala ,  Jamshed Jalal ,  Antony John Harris ,  Jeffrey Carl Defilippi ,  Anitha Kona ,  Bruce James Mathewson

IPC: G06F13/38 ,  G06F13/40

Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path. For a selected layer of the multiple layers, the protocol conversion circuitry provides, within the gateway component, upper selected layer circuitry to implement a first portion of functionality of the selected layer, where the first portion comprises at least protocol dependent functionality of the selected layer. It also provides, within the controller, lower selected layer circuitry to implement a remaining portion of the functionality of the selected layer, the remaining portion comprising only protocol independent functionality of the selected layer.

公开(公告)号：US20220308997A1

公开(公告)日：2022-09-29

申请号：US17212804

申请日：2021-03-25

Applicant: Arm Limited

Inventor： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

IPC: G06F12/0815 ,  G06F13/40

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

公开(公告)号：US20220164288A1

公开(公告)日：2022-05-26

申请号：US17102997

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P. Ringe ,  Mukesh Patel ,  Sakshi Verma

IPC: G06F12/0815

Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.

公开(公告)号：US11269773B2

公开(公告)日：2022-03-08

申请号：US16595863

申请日：2019-10-08

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Andrew John Turner

IPC: G06F9/52 ,  G06F9/30 ,  G06F15/78 ,  G06F13/42 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0815

Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.

公开(公告)号：US20210058335A1

公开(公告)日：2021-02-25

申请号：US16550018

申请日：2019-08-23

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Kishore Kumar Jagadeesha

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/46 ,  H04L12/835

Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.

公开(公告)号：US10917198B2

公开(公告)日：2021-02-09

申请号：US16027864

申请日：2018-07-05

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Tushar P. Ringe

IPC: H04L29/08 ,  H04L1/16

Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

公开(公告)号：US20200301854A1

公开(公告)日：2020-09-24

申请号：US16361728

申请日：2019-03-22

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Tushar P. Ringe ,  Mukesh Patel ,  Jamshed Jalal ,  Ashok Kumar Tummala ,  Mark David Werkheiser

IPC: G06F12/14 ,  G06F12/0817 ,  G06F9/54

Abstract: A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.

公开(公告)号：US10282297B2

公开(公告)日：2019-05-07

申请号：US15427320

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

Abstract: A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

公开(公告)号：US12242399B2

公开(公告)日：2025-03-04

申请号：US17678174

申请日：2022-02-23

Applicant: Arm Limited

Inventor： Jacob Joseph ,  Tessil Thomas ,  Arthur Brian Laughton ,  Anitha Kona ,  Jamshed Jalal

IPC: G06F13/00 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/1045 ,  G06F13/16

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.