Invention Grant
- Patent Title: Memory cell architecture for multilevel cell programming
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Application No.: US16045526Application Date: 2018-07-25
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Publication No.: US10311954B2Publication Date: 2019-06-04
- Inventor: Mario Allegra , Mattia Boniardi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C13/00 ; G11C11/56 ; H01L45/00 ; H01L27/24

Abstract:
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.
Public/Granted literature
- US20180358094A1 MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING Public/Granted day:2018-12-13
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