Invention Grant
- Patent Title: System and method for a floating-point format for digital signal processors
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Application No.: US15723924Application Date: 2017-10-03
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Publication No.: US10324688B2Publication Date: 2019-06-18
- Inventor: Yuanbin Guo , Tong Sun , Weizhong Chen
- Applicant: Futurewei Technologies, Inc.
- Applicant Address: US TX Plano
- Assignee: FUTUREWEI TECHNOLOGIES, INC.
- Current Assignee: FUTUREWEI TECHNOLOGIES, INC.
- Current Assignee Address: US TX Plano
- Agency: Slater Matsil, LLP
- Main IPC: G06F7/483
- IPC: G06F7/483

Abstract:
An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.
Public/Granted literature
- US20180046435A1 System and Method for a Floating-Point Format for Digital Signal Processors Public/Granted day:2018-02-15
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