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公开(公告)号：US11334355B2
公开(公告)日：2022-05-17
申请号：US15586937
申请日：2017-05-04
Applicant: Futurewei Technologies, Inc.
Inventor： Alan Gatherer , Sushma Wokhlu , Peter Yan , Ywhpyng Harn , Ashish Rai Shrivastava , Tong Sun , Lee Dobson McFearin
IPC: G06F9/38 , G06F9/30 , G06F13/16 , G06F12/0853 , G06F9/46 , G06F12/0884 , G06F3/06 , G06F12/0868 , G06F12/0855
Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
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2.发明申请公开(公告)号：US20170132003A1
公开(公告)日：2017-05-11
申请号：US14937093
申请日：2015-11-10
Applicant: Futurewei Technologies, Inc.
Inventor： Tong Sun , Ying Xu , Weizhong Chen
CPC classification number: G06F9/3851 , G06F9/3853 , G06F9/3889 , G06F9/3891 , G06F9/5027 , G06F2209/507 , Y02D10/22
Abstract: A system and method of hardware multithreading in VLIW DSPs includes an instruction fetch and dispatch unit, a plurality of program control units coupled to the instruction fetch and dispatch unit, a plurality of function units coupled to the plurality of program control units, and a mode control unit coupled to the function units and the program control units, the mode control unit configured to dynamically organize the plurality of function units and the plurality of program control units into one or more threads, each thread comprising a program control of the plurality of program control units and a subset of the plurality of function units.
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公开(公告)号：US10185606B2
公开(公告)日：2019-01-22
申请号：US15096966
申请日：2016-04-12
Applicant: Futurewei Technologies, Inc.
Inventor： Peter Yan , Alan Gatherer , Alex Elisa Chandra , Lee Dobson Mcfearin , Mark Brown , Debashis Bhattacharya , Fang Yu , Xingfeng Chen , Yan Bei , Ke Ning , Chushun Huang , Tong Sun , Xiaotao Chen
Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
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公开(公告)号：US20180217838A1
公开(公告)日：2018-08-02
申请号：US15422014
申请日：2017-02-01
Applicant: Futurewei Technologies, Inc.
Inventor： Weizhong Chen , Tong Sun , Bin Yang
IPC: G06F9/30 , H04W88/10 , G06F12/0875
CPC classification number: G06F9/30036 , G06F9/3001 , G06F9/30043 , G06F9/3005 , G06F9/3012 , G06F9/3016 , G06F9/3885 , G06F12/0875 , G06F2212/452 , H04W88/10
Abstract: An apparatus comprises a central processor that outputs a first control signal to data organizers that organizes and moves data and a second control signal to vector processors that receives a first and second set of data from the data organizers. A first vector processor includes a first instruction circuit that executes a first plurality of vector functions and a second instruction circuit that executes a second plurality of vector functions. A first vector function is selected from the first plurality of vector functions to process the first set of data in response to the second control signal. Similarly, a second vector function is selected from the second plurality of vector functions to process the second set of data in response to the second control signal.
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公开(公告)号：US09841999B2
公开(公告)日：2017-12-12
申请号：US14815871
申请日：2015-07-31
Applicant: Futurewei Technologies, Inc.
Inventor： Weizhong Chen , Bin Yang , Tong Sun
CPC classification number: G06F9/5016 , G06F9/5027 , G06F9/5094 , Y02D10/22
Abstract: An apparatus and method are provided for allocating resources to a plurality of threads to perform a service. In use, a request for service is received. At least one of a plurality of resources is allocated to the threads. Further, the service is performed with the threads, utilizing the allocated at least one resource.
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Patent Agency Ranking
6.发明申请APPARATUS AND METHOD FOR ALLOCATING RESOURCES TO THREADS TO PERFORM A SERVICE 有权用于分配资源用于螺纹以执行服务的装置和方法公开(公告)号：US20170031717A1
公开(公告)日：2017-02-02
申请号：US14815871
申请日：2015-07-31
Applicant: Futurewei Technologies, Inc.
Inventor： Weizhong Chen , Bin Yang , Tong Sun
IPC: G06F9/50
CPC classification number: G06F9/5016 , G06F9/5027 , G06F9/5094 , Y02D10/22
Abstract: An apparatus and method are provided for allocating resources to a plurality of threads to perform a service. In use, a request for service is received. At least one of a plurality of resources is allocated to the threads. Further, the service is performed with the threads, utilizing the allocated at least one resource.
Abstract translation: 提供了一种用于向多个线程分配资源以执行服务的装置和方法。 在使用中，接收到服务请求。 多个资源中的至少一个被分配给线程。 此外，利用所分配的至少一个资源，利用线程执行服务。
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公开(公告)号：US10324688B2
公开(公告)日：2019-06-18
申请号：US15723924
申请日：2017-10-03
Applicant: Futurewei Technologies, Inc.
Inventor： Yuanbin Guo , Tong Sun , Weizhong Chen
IPC: G06F7/483
Abstract: An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.
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公开(公告)号：US20140136582A1
公开(公告)日：2014-05-15
申请号：US13674698
申请日：2012-11-12
Applicant: FUTUREWEI TECHNOLOGIES, INC.
Inventor： Weizhong Chen , Yuanpei Jiao , Tong Sun
IPC: G06F7/02
Abstract: A method for scaling a plurality of data values includes storing a first subset of data values of the plurality of data values into a first vector register, determining a maximum data value of the first subset of data values, and storing the greater of the maximum data value and a value stored in a scalar register to the scalar register. Each data value of the subset of data values is stored in a different element of the first vector register. The method further includes determining an adjustment factor based on the value stored in the scalar register and adjusting each data value of the plurality of data values by the adjustment factor.
Abstract translation: 用于缩放多个数据值的方法包括将多个数据值的数据值的第一子集存储到第一向量寄存器中，确定数据值的第一子集的最大数据值，并存储更大的最大数据 值和存储在标量寄存器中的值到标量寄存器。 数据子集的每个数据值被存储在第一向量寄存器的不同元素中。 该方法还包括基于存储在标量寄存器中的值来确定调整因子，并且通过调节因子来调整多个数据值的每个数据值。
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公开(公告)号：US20180321939A1
公开(公告)日：2018-11-08
申请号：US15586937
申请日：2017-05-04
Applicant: Futurewei Technologies, Inc.
Inventor： Alan Gatherer , Sushma Wokhlu , Peter Yan , Ywhpyng Harn , Ashish Rai Shrivastava , Tong Sun , Lee Dobson McFearin
CPC classification number: G06F9/3016 , G06F3/061 , G06F3/0656 , G06F3/0673 , G06F9/3802
Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
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公开(公告)号：US20180046435A1
公开(公告)日：2018-02-15
申请号：US15723924
申请日：2017-10-03
Applicant: Futurewei Technologies, Inc.
Inventor： Yuanbin Guo , Tong Sun , Weizhong Chen
IPC: G06F7/483
CPC classification number: G06F7/483
Abstract: An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.
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