A chip-stack structure including a first chip and a second chip located on the first chip is provided. The first chip includes a first substrate, a first interconnect structure, a first pad, and a first contact conductor. The first interconnect structure is located on a first surface of the first substrate. The first pad is located on the first interconnect structure. The first contact conductor is located in the first substrate and exposed on a second surface of the first substrate opposite to the first surface. The second chip includes a second substrate, a second interconnect structure, a second pad, and a second contact conductor. The second interconnect structure is located on the second substrate. The second pad is located on the second interconnect structure. The second contact conductor is located in the second substrate, wherein the first contact conductor is directly physically in contact with the second pad.