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    SEMICONDUCTOR STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20230005833A1

    公开(公告)日：2023-01-05

    申请号：US17943215

    申请日：2022-09-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hung Chen ,  Ming-Tse Lin

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L27/01

    Abstract: A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

    SEMICONDUCTOR STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20220084928A1

    公开(公告)日：2022-03-17

    申请号：US17073392

    申请日：2020-10-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hung Chen ,  Ming-Tse Lin

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L27/01

    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other.

    CHIP-STACK STRUCTURE
    5.
    发明申请
    CHIP-STACK STRUCTURE 有权

    公开(公告)号：US20210057368A1

    公开(公告)日：2021-02-25

    申请号：US17075530

    申请日：2020-10-20

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Tse Lin

    IPC: H01L23/00 ,  H01L25/065 ,  H05K3/46 ,  H01L23/48 ,  H01L25/00 ,  H01L27/06

    Abstract: The present disclosure provides a manufacturing method of a die-stack structure including follow steps. A first wafer including a first die is provided, wherein the first die includes a first substrate material layer, a first interconnect structure, and a first pad, and the first interconnect structure and the first pad are formed on the first substrate material layer in order, and the first substrate material layer has a first contact conductor disposed therein. a first contact conductor is disposed in the first substrate material layer. A second wafer including a second die is provided, wherein the second die includes a second substrate material layer, a second interconnect structure, and a second pad, and the second interconnect structure and the second pad are formed on the second substrate material layer in order, and the second substrate material layer has a second contact conductor disposed therein. A portion of the first substrate material layer is removed to form a first substrate, wherein the first contact conductor is exposed to a surface of the first substrate away from the first interconnect structure. The second wafer is covered on the first substrate such that the first contact conductor is directly physically in contact with the second pad.

    METHOD FOR FABRICATION SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD FOR FABRICATION SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170330820A1

    公开(公告)日：2017-11-16

    申请号：US15663679

    申请日：2017-07-28

    Applicant: United Microelectronics Corp.

    Inventor： Kuei-Sheng Wu ,  Ming-Tse Lin

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532

    CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2225/06541

    Abstract: A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.

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