Invention Grant
- Patent Title: Formation method of interconnection structure of semiconductor device
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Application No.: US15633992Application Date: 2017-06-27
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Publication No.: US10332787B2Publication Date: 2019-06-25
- Inventor: Chung-Wen Wu , Chien-Wen Chiu , Chien-Chung Chen , Shiu-Ko Jangjian
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/768

Abstract:
Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.
Public/Granted literature
- US20180374744A1 FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE Public/Granted day:2018-12-27
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