公开(公告)号：US09837306B2

公开(公告)日：2017-12-05

申请号：US15145369

申请日：2016-05-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Wen Wu ,  Shiu-Ko Jangjian ,  Chien-Wen Chiu ,  Chien-Chung Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

公开(公告)号：US10332787B2

公开(公告)日：2019-06-25

申请号：US15633992

申请日：2017-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wen Wu ,  Chien-Wen Chiu ,  Chien-Chung Chen ,  Shiu-Ko Jangjian

IPC: H01L21/76 ,  H01L21/768

Abstract: Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.