公开(公告)号：US10861788B2

公开(公告)日：2020-12-08

申请号：US16229818

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

公开(公告)号：US09837306B2

公开(公告)日：2017-12-05

申请号：US15145369

申请日：2016-05-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Wen Wu ,  Shiu-Ko Jangjian ,  Chien-Wen Chiu ,  Chien-Chung Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

公开(公告)号：US20140264902A1

公开(公告)日：2014-09-18

申请号：US13794999

申请日：2013-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract translation: 本公开涉及一种半导体结构及其制造方法，其中间隔元件邻近嵌入在第一互连层的第一电介质层中的金属体形成。 相对于金属体的边缘不对准的通孔形成在第二互连层中的第二介电材料中，第二互连层设置在第一互连层上并且填充有电耦合到金属体的导电材料。 该方法允许形成互连结构，而不会遇到通过第一互连层的电介质材料中的子结构缺陷所呈现的各种问题，以及消除常规间隙填充金属化问题。

公开(公告)号：US10170420B2

公开(公告)日：2019-01-01

申请号：US15496491

申请日：2017-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

公开(公告)号：US20170229397A1

公开(公告)日：2017-08-10

申请号：US15496491

申请日：2017-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

公开(公告)号：US20160218038A1

公开(公告)日：2016-07-28

申请号：US15088292

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract translation: 本公开涉及一种半导体结构及其制造方法，其中间隔元件邻近嵌入在第一互连层的第一电介质层中的金属体形成。 相对于金属体的边缘不对准的通孔形成在第二互连层中的第二介电材料中，第二互连层设置在第一互连层上并且填充有电耦合到金属体的导电材料。 该方法允许形成互连结构，而不会遇到通过第一互连层的电介质材料中的子结构缺陷所呈现的各种问题，以及消除常规间隙填充金属化问题。

公开(公告)号：US20220359274A1

公开(公告)日：2022-11-10

申请号：US17869177

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wen Wu ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/762 ,  H01L23/48 ,  H01L51/00

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

公开(公告)号：US10332787B2

公开(公告)日：2019-06-25

申请号：US15633992

申请日：2017-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wen Wu ,  Chien-Wen Chiu ,  Chien-Chung Chen ,  Shiu-Ko Jangjian

IPC: H01L21/76 ,  H01L21/768

Abstract: Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.

公开(公告)号：US09640435B2

公开(公告)日：2017-05-02

申请号：US15088292

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

公开(公告)号：US20210074636A1

公开(公告)日：2021-03-11

申请号：US16952345

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.