Invention Grant
- Patent Title: 3D package having edge-aligned die stack with direct inter-die wire connections
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Application No.: US15721703Application Date: 2017-09-29
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Publication No.: US10332899B2Publication Date: 2019-06-25
- Inventor: Yi Xu , Florence Pon , Yong She
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP.
- Main IPC: H01L27/112
- IPC: H01L27/112 ; G06F17/50 ; H01L21/768 ; H01L23/525 ; H03K19/177
Abstract:
An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.
Public/Granted literature
- US20190103409A1 3D PACKAGE HAVING EDGE-ALIGNED DIE STACK WITH DIRECT INTER-DIE WIRE CONNECTIONS Public/Granted day:2019-04-04
Information query
IPC分类:
